IP Library Granted Patent US 12,443,373
Granted Patent B2
US 12,443,373 · App. 18/628,917 · Granted Oct 14, 2025

Near memory processing dual in-line memory module and method for operating the same

Inventors: Eldho Mathew Pathiyakkara Thombra (Bengaluru, IN); Prashant Vishwanath Mahendrakar (Bengaluru, IN); Jin In So (Hwaseong-si, KR); Jong-Geon Lee (Seoul, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G06F3/0659G06F3/0604G06F3/0679
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Quick Facts
Patent No.
US 12,443,373
App. No.
18/628,917
Granted
Oct 14, 2025
Kind
B2
Abstract

A method for operating a Near Memory Processing (NMP) Dual In-line Memory Module (DIMM) for DIMM-to-DIMM communication is provided. The NMP DIMM includes one or more ports for communicative connection to other NMP DIMMs. The method includes parsing, by one NMP DIMM, a NMP command received from a processor of a host platform, identifying data dependencies on one or more other NMP DIMMs based on the parsing, establishing communication with the one or more other NMP DIMMs through one or more ports of the one NMP DIMM, receiving data from the one or more other NMP DIMMs through one or more ports of the one NMP DIMM, processing the NMP command using the data received from one of the one or more other NMP DIMMs and data present in the one NMP DIMM, and sending a NMP command completion notification to the processor of the host platform.

Claims (46)

1. A system for Dual In-line Memory Module (DIMM)-to-DIMM communication, the system comprising:

a plurality of Near Memory Processing (NMP) Dual In-line Memory Modules (DIMMs), each NMP DIMM comprising a processing node and one or more ports, each of the one or more ports configured to establish communication with a port among one or more ports of another NMP DIMM of the plurality of NMP DIMMs; and

a processor of a host platform configured to:

identify data dependencies to offload a NMP command to one NMP DIMM among the plurality of NMP DIMMs; and

initiate aggregation of data to the one NMP DIMM by queuing data read requests to the one NMP DIMM,

wherein the processing node of the one NMP DIMM is configured to:

receive data directly from one or more ports of one or more other NMP DIMMs among the plurality of NMP DIMMs through the one or more ports of the one NMP DIMM;

receive the NMP command from the processor of the host platform;

process the NMP command received from the processor of the host platform using the data received from at least one of the one or more other NMP DIMMs and data present in the one NMP DIMM; and

send a NMP command completion notification to the processor of the host platform.

2. The system as claimed in claim 1 , wherein the one NMP DIMM comprises one port, and

wherein the processing node of the one NMP DIMM is configured to:

communicatively connect the one NMP DIMM and a first NMP DIMM of the one or more other NMP DIMMs through the one port.

3. The system as claimed in claim 1 , wherein the one NMP DIMM comprises a first port and a second port, and

the processing node of the one NMP DIMM is further configured to:

communicatively connect the one NMP DIMM and a first NMP DIMM of the one or more other NMP DIMMs through the first port; and

communicatively connect the one NMP DIMM and a second NMP DIMM of the one or more other NMP DIMMs through the second port.

4. The system as claimed in claim 3 , wherein the one NMP DIMM comprises a switch, and

wherein the processing node of the one NMP DIMM is configured to:

select one of the first port and the second port using the switch.

5. The system as claimed in claim 1 , wherein one of the one or more ports of each of the plurality of NMP DIMMs is communicatively connected to at least one remote server through an external switch for accessing data.

6. The system as claimed in claim 1 , wherein the processing node of the one NMP DIMM is further configured to receive data from the one or more other NMP DIMMs based on the queued data read requests.

7. The system as claimed in claim 1 , wherein the processing node of the one NMP DIMM is further configured to establish direct communication with the one or more ports of the one or more other NMP DIMMs among the plurality of NMP DIMMs through the one or more ports of the one NMP DIMM.

8. A device comprising a first Near Memory Processing (NMP) Dual In-line Memory Module (DIMM) configured with a DIMM-to-DIMM communication with a plurality of NMP DIMMs including a second NMP DIMM, the first NMP DIMM comprising:

a first processing node; and

a first port,

wherein the first processing node of the first NMP DIMM is configured to:

receive a NMP command from a processor of a host platform configured to communicate with the first NMP DIMM and the second NMP DIMM;

establish direct communication with a second port of the second NMP DIMM through the first port of the first NMP DIMM based on a data dependency on the second NMP DIMM corresponding to the NMP command received from the host platform;

receive data directly from the second port of the second NMP DIMM through the first port of the first NMP DIMM;

process the NMP command based on the data received from the second NMP DIMM and data stored in the first NMP DIMM; and

send a notification to the host platform based on completing the NMP command.

9. The device as claimed in claim 8 , wherein the first processing node of the first NMP DIMM is further configured to:

parse the NMP command received from the processor of the host platform; and

identify the data dependency on the second NMP DIMM, based on the parsed NMP command.

10. The device as claimed in claim 8 , wherein:

the NMP command is received from the host platform to offload the NMP command to the first NMP DIMM based on identifying the data dependency on the second NMP DIMM by the host platform; and

data read requests are queued to the first NMP DIMM by the host platform to initiate aggregation of data to the first NMP DIMM.

11. The device as claimed in claim 10 , wherein the first processing node of the first NMP DIMM is further configured to receive data from the second NMP DIMM based on the queued data read requests.

12. The device as claimed in claim 8 , wherein the first processing node of the first NMP DIMM is further configured to communicatively connect the first NMP DIMM and the second NMP DIMM through the first port.

13. The device as claimed in claim 8 , wherein the first NMP DIMM further comprises a third port, and the plurality of NMP DIMMs further include a third NMP DIMM,

wherein the first processing node of the first NMP DIMM is further configured to:

communicatively connect the first NMP DIMM and the second NMP DIMM through the first port; and

communicatively connect the first NMP DIMM and the third NMP DIMM through the third port.

14. The device as claimed in claim 13 , wherein the first NMP DIMM further comprises a switch, and

wherein the first processing node of the first NMP DIMM is further configured to select one of the first port and the third port using the switch.

Priority Claims (1)
IN 202141022122 · May 17, 2021 · national
Continuity (2)
Continuation 17746562 · May 17, 2022
Related Publication 20240256185A1 · Aug 1, 2024
References Cited (31)
US 3516069A · Bray et al. · 1970 [cited by applicant]
US 4394726A · Kohl · 1983 [cited by applicant]
US 4600986A · Scheuneman et al. · 1986 [cited by applicant]
US 10915544B2 · Greene et al. · 2021 [cited by applicant]
US 10936891B2 · Kim et al. · 2021 [cited by applicant]
US 11977780B2 · Pathiyakkara Thombra · 2024 [cited by examiner]
US 20050278502A1 · Hundley · 2005 [cited by applicant]
US 20050289287A1 · Shin et al. · 2005 [cited by applicant]
US 20070030814A1 · Shin et al. · 2007 [cited by applicant]
US 20090307416A1 · Luo et al. · 2009 [cited by applicant]
US 20170005438A1 · Benedict et al. · 2017 [cited by applicant]
US 20180329853A1 · Vijayrao et al. · 2018 [cited by applicant]
US 20190205244A1 · Smith · 2019 [cited by applicant]
US 20190213148A1 · Nale et al. · 2019 [cited by applicant]
US 20190286554A1 · Berke et al. · 2019 [cited by applicant]
US 20200159584A1 · Cho et al. · 2020 [cited by applicant]
US 20210034294A1 · Sudarmani et al. · 2021 [cited by applicant]
US 20210064234A1 · Zhang et al. · 2021 [cited by applicant]
US 20210390049A1 · Kim et al. · 2021 [cited by applicant]
US 20230004489A1 · Talanki et al. · 2023 [cited by applicant]
US 20230026505A1 · Lee et al. · 2023 [cited by applicant]
US 20230124520A1 · Zhong et al. · 2023 [cited by applicant]
US 20230127869A1 · Tai et al. · 2023 [cited by applicant]
US 20230400985A1 · Kim et al. · 2023 [cited by applicant]
US 20230418474A1 · Kim et al. · 2023 [cited by applicant]
C. H. Kim et al., “Silent-PIM: Realizing the Processing-in-Memory Computing With Standard Memory Requests,” in IEEE Transactions on Parallel and Distributed Systems, vol. 33, No. 2, pp. 251-262, Feb. 1, 2022, doi: 10.11… [cited by examiner]
W. J. Lee, C. H. Kim, Y. Paik and S. W. Kim, “PISA-DMA: Processing-in-Memory Instruction Set Architecture Using DMA,” in IEEE Access, vol. 11, pp. 8622-8632, 2023, doi: 10.1109/ACCESS.2023.3238812 (Year: 2023). [cited by examiner]
J. Kim, S. Y. Kim and S. W. Kim, “Supporting Multi-Channels to DRAM-based PIM Execution for Boosting the Performance,” 2024 International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan… [cited by examiner]
Y. Zou and M. Lin, “FERMAT: FPGA-Accelerated Heterogeneous Computing Platform Near NVMe Storage,” 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Orlando, FL, USA, 2… [cited by examiner]
Processing in Memory: Chips to Petaflops; Kogge et al.; In Workshop on Mixing Logic and DRAM: Chips that Compute and Remember at ISCA '97; 1997; retrieved from http://www.cs.ucf.edu/courses/cda5106/summer02/papers/kogge… [cited by applicant]
Communication issued on Oct. 19, 2023 by the Intellectual Property India in Indian Patent Application No. 202141022122. [cited by applicant]