IP Library › Granted Patent US 12,443,455
Granted Patent B2
US 12,443,455 · App. 17/774,540 · Granted Oct 14, 2025

Electronic control device

Inventors: Masashi Mizoguchi (Tokyo, JP); Fumio Narisawa (Hitachinaka, JP); Hiroyuki Nakamura (Hitachinaka, JP); Tasuku Ishigooka (Tokyo, JP); Yuki Tanaka (Tokyo, JP)
Assignee: HITACHI ASTEMO, LTD.
G06F9/5038G06F9/4806G06F11/3419G06F2209/5021
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Quick Facts
Patent No.
US 12,443,455
App. No.
17/774,540
Granted
Oct 14, 2025
Kind
B2
Abstract

To appropriately execute a task by an electronic control device including a processor having a plurality of cores. An ECU 100 includes a multi-core CPU having a plurality of cores that execute a first task that has an execution time that varies depending on a processing amount every predetermined cycle and a second task that is higher in priority than the first task and is prohibited from being interrupted. The second task is set to be inexecutable simultaneously between the plurality of cores. A task allocation unit 11 generates a first plan. A diagnosis task planning unit 12 generates a second plan. Task processing units 10 a and 10 b execute the first task based on the first plan. A diagnosis task correction unit 13 times a delay time of the first task executed by the task processing units 10 a and 10 b , and postpones the second task of the second plan to the subsequent executable timing in accordance with the timed delay time. A diagnosis unit 14 executes the second task for each core based on the second plan corrected by the diagnosis task correction unit 13.

Claims (24)

1. An electronic control device comprising:

a processor that includes a plurality of cores configured to execute:

first tasks that has an execution time that varies depending on a processing amount every predetermined cycle; and

a second task that is lower in priority than the first tasks and is prohibited from being interrupted, wherein the second task comprises a core diagnosis task that has a constraint in failure detection time for the plurality of cores, wherein the constraint in failure detection time corresponds to a constraint on a time interval to detect a failure after abnormality occurs in one of the plurality of cores,

wherein the second task is set to be inexecutable simultaneously between the plurality of cores, and

the electronic control device is configured to generate a first plan in which a respective first task of the first tasks is allocated to each of the cores,

the electronic control device is configured to generate a second plan in which the second task is allocated to each of the cores at an executable timing at which the first task is not being executed,

the plurality of cores are configured to execute the first tasks based on the first plan,

the electronic control device is configured to determine that when a delay in the execution of the first executed tasks has occurred by a delay amount of time to thereby postpone, in accordance with a shift amount of time, the future executable timing periods of the second task in a correction to the second plan, and

the electronic control device is configured to execute the second task for each of the cores based on the corrected second plan, wherein the electronic control device controlling a vehicle,

wherein the electronic control device is configured to change the failure detection time in accordance with a travel environment of the vehicle.

2. The electronic control device according to claim 1 , comprising:

a computer that comprises the processor; and

a communication channel that connects the computer and another computer, wherein

the respective first task comprises a communication task transmitted and received between the computer and the other computer via the communication channel.

3. The electronic control device according to claim 1 ,

wherein the delay time is a startup deviation time of the plurality of cores or an actual required execution time of the first tasks.

4. The electronic control device according to claim 1 , wherein the core diagnosis task is postponed to an earliest executable timing among a plurality of the subsequent executable timings.

5. The electronic control device according to claim 1 ,

wherein

the plurality of cores include a first core and a second core, and

in response to determining that execution timings of the core diagnosis task postponed in the first core and the core diagnosis task of the second core overlap, the electronic control device is configured to postpone the core diagnosis task of the second core to the subsequent executable timing so that the second task is set to be inexecutable simultaneously between the plurality of cores.

6. The electronic control device according to claim 5 , wherein one of the first core and second core is configured to transmit the core diagnosis task to the other, causes the other to transmit a reply result to the one and compare a transmitted reply result with a predetermined expectation result, and diagnoses a failure of the first core and the second core.

7. The electronic control device according to claim 1 , wherein the electronic control device is configured to first allocate the core diagnosis task to a core that executes a core diagnosis task in which the execution time is longer than that of another task of the plurality of core diagnosis tasks.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2025
From: MIZOGUCHI, MASASHI; NARISAWA, FUMIO; NAKAMURA, HIROYUKI; ISHIGOOKA, TASUKU; TANAKA, YUKI
To: HITACHI ASTEMO, LTD.
Reel/Frame 072156/0947 →
Priority Claims (1)
JP 2019-216011 · Nov 29, 2019 · national
Continuity (1)
Related Publication 20220398135A1 · Dec 15, 2022
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