Dynamic phase adjustment for high speed clock signals
A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value. The clock generator circuit may be implemented in a clock domain of a system along with one or more other clock generator circuits that each generate an output clock based on a reference clock generated by a reference clock source, such as a phase-locked loop.
1. A circuit comprising:
clock divider circuitry having a first control input and a first output, and including frequency divider circuitry configured to apply a divide ratio to a reference clock to provide a first clock signal at the first output;
a digital delay circuitry having an input coupled to the first output, and having a second control input and a second output;
an analog delay circuitry having an input coupled to the second output, and having a third control input and a clock output; and
control circuitry having outputs coupled to the first, second, and third control inputs, the control circuitry configured, responsive to an indication to provide an adjusted output clock signal at the clock output, to:
control the frequency divider circuitry to adjust the divide ratio applied to the reference clock to provide the first clock signal;
control the digital delay circuitry to delay the first clock signal to provide a second clock signal; and
control the analog delay circuitry to delay the second clock signal to provide the adjusted output clock signal.
2. The circuit of claim 1 , wherein the frequency divider circuitry includes:
a synchronous counter having an input to receive the reference clock and having outputs; and
combinational logic having inputs coupled to the outputs of the synchronous counter and an output coupled to the input of the digital delay circuitry, the combinational logic configured to provide the first clock signal responsive to the divide ratio.
3. The circuit of claim 1 , wherein the digital delay circuitry includes:
a first latch circuit having an input coupled to the first output and having a first output;
a second latch circuit having an input coupled to the output of the first latch circuit, and having a second output; and
a multiplexer having a first input coupled to the first output, a second input coupled to the second output, and an output coupled to the input of the analog delay circuitry, and the control circuitry is configured to control the multiplexer to select the first or second output to provide the second clock signal responsive to the indication to provide the adjusted output clock signal.
4. The circuit of claim 3 , wherein the digital delay circuitry is configured to delay the first clock signal by a first increment value, and the analog delay circuitry is configured to delay the second clock signal by a second increment value that is less than the first increment value.
5. The circuit of claim 1 , wherein the analog delay circuitry includes:
a phase interpolator having an input coupled to the second output, and wherein the control circuitry is configured to control the phase interpolator to delay the second clock signal to provide the adjusted output clock signal.
6. A circuit comprising:
clock divider circuitry having a first control input and an output;
a digital delay circuitry having a second control input, and including:
a first latch circuit having an input coupled to the output of the clock divider circuitry and having an output;
a second latch circuit having an input coupled to the output of the first latch circuit, and having an output; and
a multiplexer having a first input coupled to the output of the first latch circuit, a second input coupled to the output of the second latch circuit, and an output;
an analog delay circuitry having an input coupled to the output of the multiplexer, and having a third control input and a clock output; and
control circuitry having outputs coupled to the first, second, and third control inputs, the control circuitry configured, responsive to an indication to provide an adjusted output clock signal at the clock output, to:
control the clock divider circuitry to provide a first clock signal that is based on a reference clock signal;
control the multiplexer to select the first or second inputs of the multiplexer to provide a second clock signal at the output of the multiplexer that is delayed relative to the first clock signal; and
control the analog delay circuitry to delay the second clock signal to provide the adjusted output clock signal.
7. The circuit of claim 6 , wherein the clock divider circuitry includes frequency divider circuitry configured to apply a divide ratio to the reference clock signal to provide the first clock signal, and the control circuitry is configured to control the frequency divider circuitry to adjust the divide ratio responsive to the indication to provide the adjusted output clock signal.
8. The circuit of claim 7 , wherein the frequency divider circuitry includes:
a synchronous counter having an input to receive the reference clock signal and having outputs; and
combinational logic having inputs coupled to the outputs of the synchronous counter and an output coupled to the input of the digital delay circuitry, the combinational logic configured to provide the first clock signal responsive to the divide ratio.
9. The circuit of claim 6 , wherein the digital delay circuitry is configured to delay the first clock signal by a first increment value, and the analog delay circuitry is configured to delay the second clock signal by a second increment value that is less than the first increment value.
10. The circuit of claim 6 , wherein the analog delay circuitry includes:
a phase interpolator having an input coupled to the output of the multiplexer, and wherein the control circuitry is configured to control the phase interpolator to delay the second clock signal to provide the output adjusted clock signal.
11. A circuit comprising:
clock divider circuitry having a first control input and a first output;
a digital delay circuitry having an input coupled to the first output, and having a second control input and a second output;
an analog delay circuitry including a phase interpolator having an input coupled to the second output, the phase interpolator having a third control input and a clock output; and
control circuitry having outputs coupled to the first, second, and third control inputs, the control circuitry configured, responsive to an indication to provide an adjusted output clock signal at the clock output, to:
control the clock divider circuitry to provide a first clock signal that is based on a reference clock signal;
control the digital delay circuitry to delay the first clock signal to provide a second clock signal; and
control the phase interpolator to delay the second clock signal to provide the adjusted output clock signal.
12. The circuit of claim 11 , wherein the clock divider circuitry includes frequency divider circuitry configured to apply a divide ratio to the reference clock signal to provide the first clock signal, and the control circuitry is configured to control the frequency divider circuitry to adjust the divide ratio responsive to the indication to provide the adjusted output clock signal.
13. The circuit of claim 12 , wherein the frequency divider circuitry includes:
a synchronous counter having an input to receive the reference clock signal and having outputs; and
combinational logic having inputs coupled to the outputs of the synchronous counter and an output coupled to the input of the digital delay circuitry, the combinational logic configured to provide the first clock signal responsive to the divide ratio.
14. The circuit of claim 11 , wherein the digital delay circuitry includes:
a first latch circuit having an input coupled to the first output and having a first output;
a second latch circuit having an input coupled to the output of the first latch circuit, and having a second output; and
a multiplexer having a first input coupled to the first output, a second input coupled to the second output, and an output coupled to the input of the analog delay circuitry, and the control circuitry is configured to control the multiplexer to select the first or second output to provide the second clock signal responsive to the indication to provide the adjusted output clock signal.
15. The circuit of claim 14 , wherein the digital delay circuitry is configured to delay the first clock signal by a first increment value, and the analog delay circuitry is configured to delay the second clock signal by a second increment value that is less than the first increment value.