Artificial reality systems including digital and analog control of pixel intensity
Electronic display devices include digital and analog control of pixel intensity. A digital pixel control circuit and an analog pixel control circuit are provided within each pixel. The digital pixel control circuit employs digital PWM techniques to control a number of subframes within each frame during which a driving current is supplied to a light emitting element within the pixel. The analog pixel control circuit controls the level of the driving current supplied to the light emitting element within the pixel during the frame. In one example, the digital pixel control circuit and the analog pixel control circuit may together control pixel intensity with the analog pixel control circuit providing additional in-pixel bits for increased color depth. Alternatively, the digital pixel control circuit may control pixel intensity and the analog pixel control circuit may control non-uniformity compensation.
1. A display device comprising a plurality of pixels, wherein each of the plurality of pixels comprises:
a light emitting element; and
an analog pixel control circuit that controls a level of a driving current provided to the light emitting element during two or more subframes of a frame,
wherein the analog pixel control circuit comprises a storage capacitor configured to be charged to a driving voltage controlled by m bits of an n+m-bit control word, wherein the driving voltage controls the level of the driving current provided to the light emitting element during the two or more subframes of the frame, and wherein the n+m-bit control word corresponds to a desired intensity level of a pixel for the frame and the m bits of the n+m-bit control word corresponds to a non-uniformity correction value.
2. The display device of claim 1 wherein the level of driving current controlled by the analog pixel control circuit comprises the m bits of the n+m-bit control word.
3. The display device of claim 1 , wherein each of the plurality of pixels further comprises a digital pixel control circuit, wherein the digital pixel control circuit generates a pulse width modulation (PWM) output signal that controls a number of subframes of the frame during which the driving current is provided to the light emitting element.
4. The display device of claim 3 , wherein the PWM output signal generated by the digital pixel control circuit comprises n bits of the n+m-bit control word.
5. The display device of claim 1 , wherein each of the plurality of pixels further comprises a pixel driver circuit, the pixel driver circuit comprising:
a first transistor having a first control terminal connected to receive a pulse width modulation (PWM) output signal from a digital pixel control circuit, a first input terminal, and a first output terminal connected to provide the driving current to the light emitting element; and
a second transistor having a second output terminal connected to the first input terminal of the first transistor, a second input terminal connected to a node formed by a connection between a voltage source and an output terminal of the storage capacitor, and a second control terminal connected to an input terminal of the storage capacitor.
6. The display device of claim 5 , wherein the analog pixel control circuit further comprises:
a third transistor having a third control terminal connected to receive a scan signal, an output terminal connected to a node formed by the connection between the input terminal of the storage capacitor and the second control terminal of the second transistor, and an input terminal connected to receive a control voltage corresponding to the m bits of the n+m-bit control word corresponding to the desired intensity level of the pixel for the frame.
7. An artificial reality system comprising:
a head mounted display (HMD) configured to output artificial reality content, the HMD including at least one display device comprising a plurality of pixels, wherein each of the plurality of pixels comprises:
a light emitting element; and
an analog pixel control circuit that controls a level of a driving current provided to the light emitting element during two or more subframes of a frame, wherein the analog pixel control circuit comprises a storage capacitor configured to be charged to a driving voltage controlled by m bits of an n+m-bit control word, wherein the driving voltage controls the level of the driving current provided to the light emitting element during the two or more subframes of the frame, and wherein the n+m-bit control word corresponds to a desired intensity level of a pixel for the frame and the m bits of the n+m-bit control word corresponds to a non-uniformity correction value.
8. The artificial reality system of claim 7 , wherein the level of the driving current controlled by the analog pixel control circuit comprises the m bits of the n+m-bit control word.
9. The artificial reality system of claim 7 , wherein each of the plurality of pixels further comprises a digital pixel control circuit that generates a pulse width modulation (PWM) output signal that controls a number of subframes of the frame during which the driving current is provided to the light emitting element.
10. The artificial reality system of claim 9 , wherein the digital pixel control circuit generates the PWM output signal based on n bits of the n+m-bit control word.
11. The artificial reality system of claim 7 , wherein n is greater than m.
12. The artificial reality system of claim 7 , wherein n is an integer between 5 and 10 and m is an integer between 2 and 5.
13. The artificial reality system of claim 7 , wherein a number of intensity levels defined by the n+m-bit control word is 2 n+m .
14. The artificial reality system of claim 7 , wherein each of the plurality of pixels further comprises a pixel driver circuit, the pixel driver circuit comprising:
a first transistor having a first control terminal connected to receive a pulse width modulation (PWM) output signal from a digital pixel control circuit, a first input terminal, and a first output terminal connected to provide the driving current to the light emitting element; and
a second transistor having a second output terminal connected to the first input terminal of the first transistor, a second input terminal connected to a node formed by a connection between a voltage source and an output terminal of the storage capacitor, and a second control terminal connected to an input terminal of the storage capacitor.
15. The artificial reality system of claim 14 , wherein the analog pixel control circuit further comprises:
a third transistor having a third control terminal connected to receive a scan signal, an output terminal connected to a node formed by the connection between the input terminal of the storage capacitor and the second control terminal of the second transistor, and an input terminal connected to receive a control voltage corresponding to the m bits of the n+m-bit control word corresponding to the desired intensity level of the pixel for the frame.
16. The artificial reality system of claim 14 , wherein the first transistor and the second transistor are of a same type.
17. The artificial reality system of claim 14 , wherein the first transistor and the second transistor are p-type transistors.
18. A method comprising:
controlling, with analog pixel control circuitry of each pixel of a plurality of pixels included in a display device, a level of a driving current provided to a light emitting element of a respective pixel of the plurality of pixels included in the display device during two or more subframes of a frame, wherein controlling the level of the driving current comprises:
charging a storage capacitor of the analog pixel control circuitry to a driving voltage controlled by m bits of an n+m-bit control word, wherein the n+m-bit control word corresponds to a desired intensity level of the respective pixel for the frame and the m bits of the n+m-bit control word corresponds to a non-uniformity correction value; and
controlling the level of the driving current provided to the light emitting element during the two or more subframes of the frame based on the driving voltage stored in the storage capacitor.
19. The method of claim 18 , further comprising:
generating, with digital pixel control circuitry of each pixel of the plurality of pixels included in the display device, a pulse width modulation (PWM) output signal that controls a number of subframes of the frame during which the driving current is provided to the light emitting element of the respective pixel of the plurality of pixels included in the display device.
20. The method of claim 19 , wherein the PWM output signal comprises n bits of the n+m-bit control word.