IP Library › Granted Patent US 12,450,042
Granted Patent B2
US 12,450,042 · App. 18/282,762 · Granted Oct 21, 2025

Input driven execution randomisation

Inventor: Nicholas Gildea (London, GB)
Assignee: Verimatrix UK LTD
G06F8/447G06F8/433G06F21/602H04L9/0662
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Quick Facts
Patent No.
US 12,450,042
App. No.
18/282,762
Filed
Sep 18, 2023
Granted
Oct 21, 2025
Kind
B2
Art Unit
2151
USPC
717/140
Abstract

Embodiments of systems, devices and methods for protecting computer programs against analysis and/or attacks that rely on synchronized ordering and repeatability are provided herein. Embodiments disclosed herein include receiving input source code, the source code comprising code instructions of a computer program; generating a graph structure representative of the code instructions comprising nodes representative of portions of the code instructions and links representative of dependencies between the portions of the code instructions, wherein the nodes can be traversed in a plurality of orders without invalidating the dependencies between the portions of the code instructions; constructing a plurality of function definitions based on the graph structure, each function definition configured to execute one or more nodes of the graph structure and each node of the graph structure is executable by one or more function definitions; transforming the input source code into transformed source code based on combining the graph structure and the plurality of function.

Claims (45)

1. A method of protecting a computer program against side-channel attacks, the method comprising:

receiving input source code of the computer program, the source code comprising code instructions of the computer program;

generating a graph structure representative of the code instructions, the graph structure comprising nodes representative of portions of the code instructions and links representative of dependencies between the portions of the code instructions, wherein the nodes can be traversed in a plurality of orders without invalidating the dependencies between the portions of the code instructions;

constructing a plurality of function definitions based on the graph structure, each function definition is configured to execute one or more nodes of the graph structure and each node of the graph structure is executable by one or more function definitions;

transforming the input source code into transformed source code based on combining the graph structure and the plurality of function; and

wherein the method further comprising:

identifying portions of the code instructions and constructing the nodes based on the identified portions of the code instructions;

for each code instruction, identifying dependencies between a respective portion of the code instructions based on inputs into and outputs from the respective portion of the code instructions;

generating the links based on the identified dependencies;

merging subsets of the nodes based on the dependencies between each subset of the nodes;

appending the portions of the code instructions represented by at least a first node of the subset to the code instructions represented by at least a second node of the subset;

removing the at least the second node from the graph structure; and

updating the graph structure based on the merge.

2. The method of claim 1 , wherein the input source code is transformed into the transformed source code such that the transformed source code can be executed by a target device, such that the transformed source code receives input values from the target device, selects an order of the plurality of orders for executing the graph structure based on each input value, and, based on each input value, selects a function definition from the plurality of function definitions for executing each node, where the selected order and selected function definitions are unique to each input value.

3. The method of one of claim 1 , wherein the input source code is an intermediate representation (IR) of the source code of the computer program.

4. The method of claim 3 , wherein the IR is received from a compiler.

5. The method of claim 3 , wherein the IR is a white body protected IP received from a cryptography algorithm.

6. The method of claim 5 , wherein the cryptography algorithm is a white box cryptography algorithm.

7. The method of claim 3 , wherein the IR is provided according to LLVM compiler infrastructure.

8. The method of claim 1 , further comprising:

looping through iterative mergers of subsets of the nodes until the graph structure reaches a stable state or a number of nodes of the graph structure is less than or equal to a preset number.

9. A method of protecting a computer program against side-channel attacks, the method comprising:

receiving input source code of the computer program, the source code comprising code instructions of the computer program;

generating a graph structure representative of the code instructions, the graph structure comprising nodes representative of portions of the code instructions and links representative of dependencies between the portions of the code instructions, wherein the nodes can be traversed in a plurality of orders without invalidating the dependencies between the portions of the code instructions;

constructing a plurality of function definitions based on the graph structure, each function definition is configured to execute one or more nodes of the graph structure and each node of the graph structure is executable by one or more function definitions;

transforming the input source code into transformed source code based on combining the graph structure and the plurality of function; and

wherein constructing the plurality of function definitions comprises:

randomly selecting input nodes from the nodes of the graph structure; and

constructing a sequence of functions based on the portions of the code instructions represented by the input nodes, wherein the sequence of functions is configured to execute all the portions of the code instructions of the input nodes.

10. The method of claim 9 , wherein the sequence of the code instructions is a linear sequence of functions based on aggregating the portions of the code instructions of the input nodes.

11. The method of claim 9 , wherein transforming the input source code comprises creating a pseudo random number generator and a converter configured to generate a seed value.

12. The method of claim 11 , wherein, when the computer program is executed by the target device, the transformed source code produces a seed value based on each input value, inputs the seed value into the pseudo random number generator, and iteratively selects a node of the graph structure for execution based on a result of from the pseudo random number generator, wherein each seed value is unique to each input value.

13. The method of claim 11 , wherein, when the computer program is executed by the target device, the transformed source code produces a seed value based on each input value, inputs the seed value into the pseudo random number generator, and iteratively selects a function definition from the plurality of function definition for executing a node of the graph structure, wherein each seed value is unique to each input value.

14. A system for protecting a computer program against side-channel attacks, the system comprising:

at least one memory configured to store instructions; and

at least one processor communicatively connected to the at least one memory, the at least one processor configured to execute the program to perform the method of claim 1 .

15. A non-transitory computer-readable storage media storing instruction that, when executed by a computer, cause the computer to perform the method of claim 1 .

16. A device for protecting a computer program against side-channel attacks, the device comprising:

a means for receiving input source code of the computer program, the source code comprising code instructions of the computer program;

a means for generating a graph structure representative of the code instructions, the graph structure comprising nodes representative of portions of the code instructions and links representative of dependencies between the portions of the code instructions, wherein the nodes can be traversed in a plurality of orders without invalidating the dependencies between the portions of the code instructions;

a means for constructing a plurality of function definitions based on the graph structure, each function definition is configured to execute one or more nodes of the graph structure and each node of the graph structure is executable by one or more function definitions; and

a means for transforming the input source code into transformed source code based on combining the graph structure and the plurality of function; and

wherein the means for constructing the plurality of function definitions comprises:

means for randomly selecting input nodes from the nodes of the graph structure, and

means for constructing a sequence of functions based on the portions of the code instructions represented by the input nodes, wherein the sequence of functions is configured to execute all the portions of the code instructions of the input nodes.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2023
From: GILDEA, NICHOLAS
To: VERIMATRIX UK LTD
Reel/Frame 064941/0696 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2023
From: VERIMATRIX UK LTD
To: VERIMATRIX
Reel/Frame 064941/0707 →
Continuity (3)
Provisional Application 63166738 · Mar 26, 2021
Provisional Application 63172579 · Apr 8, 2021
Related Publication 20240168740A1 · May 23, 2024
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