Driver module and display device
A driver module includes a first driver unit and a first control unit; the first driver unit includes M levels of first driver circuits; M is a positive integer; m is a positive integer less than or equal to M; the m-th level first drive signal output terminal is electrically connected to a first terminal of an m-th row first gate line, to provide an m-th level first drive signal to the m-th row first gate line; the first control unit includes M first control circuits; an m-th first control circuit included in the first control unit is electrically connected to a second terminal of the m-th row first gate line, configured to control the second terminal of the m-th row first gate line to receive an ineffective voltage signal when a voltage value of the m-th level first drive signal changes from an effective voltage to an ineffective voltage.
1. A driver module, applied to a display device including M rows of first gate lines; the driver module comprising: a first driver unit and a first control unit; wherein the first driver unit comprises M levels of first driver circuits; an m-th level first driver circuit comprises an m-th level first drive signal output terminal; M is a positive integer; m is a positive integer less than or equal to M;
the m-th level first drive signal output terminal is electrically connected to a first terminal of an m-th row first gate line, and is configured to provide an m-th level first drive signal to the m-th row first gate line through the m-th level first drive signal output terminal;
the first control unit comprises M first control circuits;
an m-th first control circuit comprised in the first control unit is electrically connected to a second terminal of the m-th row first gate line, and configured to control the second terminal of the m-th row first gate line to receive an ineffective voltage signal when a voltage value of the m-th level first drive signal changes from an effective voltage to an ineffective voltage;
the first terminal and the second terminal are opposite terminals;
wherein the m-th first control circuit is configured to control a connection between the second terminal of the m-th row first gate line and a first voltage signal terminal, under control of an m-th first control signal provided by an m-th first control terminal;
wherein the m-th level first driver circuit is electrically connected to an m-th level first output clock signal line, and configured to, under control of a potential of an m-th level first pull-up node, control the m-th level first output clock signal line to provide an m-th level first output clock signal to the m-th level first drive signal output terminal;
the m-th first control terminal is electrically connected to an m-th first control clock signal line;
the m-th first control clock signal line is configured to provide an m-th first control clock signal;
the m-th level first output clock signal and the m-th first control clock signal are reciprocal signals.
2. The driver module according to claim 1 , wherein the display device further comprises N rows of second gate lines; the driver module further comprises a second driver unit and a second control unit; the second driver unit comprises N levels of second driver circuits; an n-th level second driver circuit comprises an n-th level second drive signal output terminal; N is a positive integer; n is a positive integer less than or equal to N;
the n-th level second drive signal output terminal is electrically connected to a second terminal of an n-th row second gate line, and configured to provide an n-th level second drive signal to the n-th row second gate line through the n-th level second drive signal output terminal;
the second control unit comprises N second control circuits;
an n-th second control circuit comprised in the second control unit is electrically connected to a first terminal of the n-th row second gate line, and configured to control the first terminal of the n-th row second gate line to receive an ineffective voltage signal when a voltage value of the n-th level second drive signal changes from an effective voltage to an ineffective voltage.
3. The driver module according to claim 2 , wherein the n-th second control circuit is configured to, under control of an n-th second control signal provided by an n-th second control terminal, control a connection between the first terminal of the n-th row second gate line and a second voltage signal terminal.
4. The driver module according to claim 3 , wherein the n-th second control circuit comprises an n-th second control transistor;
a gate of the n-th second control transistor is electrically connected to the n-th second control terminal, a first pole of the n-th second control transistor is electrically connected to the first terminal of the n-th row second gate line, and a second pole of the n-th second control transistor is electrically connected to the second voltage signal terminal;
or,
wherein the n-th level second driver circuit is electrically connected to an n-th level second output clock signal line, and configured to, under control of a potential of an n-th level second pull-up node, control the n-th level second output clock signal line to provide an n-th level second output clock signal to the n-th level second drive signal output terminal;
the n-th second control terminal is electrically connected to an n-th second control clock signal line;
the n-th second control clock signal line is configured to provide an n-th second control clock signal;
the n-th level second output clock signal and the n-th second control clock signal are reciprocal signals.
5. The driver module according to claim 4 , wherein the n-th level second driver circuit comprises an n-th level second driver transistor;
a gate of the n-th level second driver transistor is electrically connected to the n-th level second pull-up node, a first pole of the n-th level second driver transistor is electrically connected to the n-th level second output clock signal line, and a second pole of the n-th level second driver transistor is electrically connected to the n-th level second drive signal output terminal;
a channel width of the n-th second control transistor is greater than or equal to a third width but less than or equal to a fourth width;
a channel length of the n-th second control transistor is greater than a channel length of the n-th level second driver transistor;
the third width is half of a channel width of the n-th level second driver transistor;
the fourth width is 1.5 times the channel width of the n-th level second driver transistor.
6. The driver module according to claim 3 , wherein the second voltage signal terminal is a direct current voltage signal terminal, and the second voltage signal terminal is configured to provide an ineffective voltage signal; or,
wherein the second voltage signal terminal is electrically connected to the n-th level second output clock signal line.
7. The driver module according to claim 1 , wherein, the m-th first control circuit comprises an m-th first control transistor;
a gate of the m-th first control transistor is electrically connected to the m-th first control terminal, a first pole of the m-th first control transistor is electrically connected to the second terminal of the m-th row first gate line, and a second pole of the m-th first control transistor is electrically connected to the first voltage signal terminal.
8. The driver module according to claim 7 , wherein the m-th level first driver circuit comprises an m-th level first driver transistor;
a gate of the m-th level first driver transistor is electrically connected to the m-th level first pull-up node, a first pole of the m-th level first driver transistor is electrically connected to the m-th level first output clock signal line, and a second pole of the m-th level first driver transistor is electrically connected to the m-th level first drive signal output terminal;
a channel width of the m-th first control transistor is greater than or equal to a first width but less than or equal to a second width;
a channel length of the m-th first control transistor is greater than a channel length of the m-th level first driver transistor;
the first width is half of a channel width of the m-th level first driver transistor;
the second width is 1.5 times the channel width of the m-th level first driver transistor.
9. The driver module according to claim 1 , wherein the first voltage signal terminal is a direct current voltage signal terminal, and the first voltage signal terminal is configured to provide an ineffective voltage signal.
10. The driver module according to claim 1 , wherein the first voltage signal terminal is electrically connected to the m-th level first output clock signal line.
11. A display device, comprising the driver module according to claim 1 .
12. A driver module, applied to a display device including M rows of first gate lines; the driver module comprising: a first driver unit and a first control unit; wherein the first driver unit comprises M levels of first driver circuits; an m-th level first driver circuit comprises an m-th level first drive signal output terminal; M is a positive integer; m is a positive integer less than or equal to M;
the m-th level first drive signal output terminal is electrically connected to a first terminal of an m-th row first gate line, and is configured to provide an m-th level first drive signal to the m-th row first gate line through the m-th level first drive signal output terminal;
the first control unit comprises M first control circuits;
an m-th first control circuit comprised in the first control unit is electrically connected to a second terminal of the m-th row first gate line, and configured to control the second terminal of the m-th row first gate line to receive an ineffective voltage signal when a voltage value of the m-th level first drive signal changes from an effective voltage to an ineffective voltage;
the first terminal and the second terminal are opposite terminals;
wherein the display device further comprises N rows of second gate lines; the driver module further comprises a second driver unit and a second control unit; the second driver unit comprises N levels of second driver circuits; an n-th level second driver circuit comprises an n-th level second drive signal output terminal; N is a positive integer; n is a positive integer less than or equal to N;
the n-th level second drive signal output terminal is electrically connected to a second terminal of an n-th row second gate line, and configured to provide an n-th level second drive signal to the n-th row second gate line through the n-th level second drive signal output terminal;
the second control unit comprises N second control circuits;
an n-th second control circuit comprised in the second control unit is electrically connected to a first terminal of the n-th row second gate line, and configured to control the first terminal of the n-th row second gate line to receive an ineffective voltage signal when a voltage value of the n-th level second drive signal changes from an effective voltage to an ineffective voltage;
wherein an a-th first control circuit comprised in the first control unit is configured to, under control of an a-th first control signal provided by an a-th first control terminal, control a connection between a second terminal of an a-th row first gate line and a first voltage signal terminal;
an a-th level first driver circuit comprised in the first driver unit is electrically connected to an a-th level first output clock signal line, and configured to, under control of a potential of an a-th level first pull-up node, control the a-th level first output clock signal line to provide an a-th level first output clock signal to an a-th level first drive signal output terminal;
a b-th level second driver circuit comprised in the second driver unit is electrically connected to a b-th level second output clock signal line, and configured to, under control of a potential of a b-th level second pull-up node, control the b-th level second output clock signal line to provide a b-th level second output clock signal to a b-th level second drive signal output terminal;
the a-th level first output clock signal line is configured to provide the a-th level first output clock signal, the b-th level second output clock signal line is configured to provide the b-th level second output clock signal, and the a-th level first output clock signal and the b-th level second output clock signal are reciprocal signals;
the a-th first control terminal is electrically connected to a b-th level second drive signal terminal comprised in the b-th level second driver circuit;
values a and b are positive integers.
13. The driver module according to claim 12 , wherein the a-th first control circuit comprises an a-th first control transistor;
a gate of the a-th first control transistor is electrically connected to the b-th level second drive signal terminal, a first pole of the a-th first control transistor is electrically connected to the second terminal of the a-th row first gate line, and a second pole of the a-th first control transistor is electrically connected to the first voltage signal terminal.
14. The driver module according to claim 12 , wherein, a c-th second control circuit comprised in the second control unit is configured to, under control of a c-th second control signal provided by a c-th second control terminal, control a connection between a first terminal of a c-th row second gate line and a second voltage signal terminal;
a c-th level second driver circuit comprised in the second driver unit is electrically connected to a c-th level second output clock signal line, and configured to, under control of a potential of a c-th level second pull-up node, control the c-th level second output clock signal line to provide a c-th level second output clock signal to a c-th level second drive signal output terminal;
a d-th level first driver circuit comprised in the first driver unit is electrically connected to a d-th level first output clock signal line, and configured to, under control of a potential of a d-th level first pull-up node, control the d-th level first output clock signal line to provide a d-th level first output clock signal to a d-th level first drive signal output terminal;
the d-th level first output clock signal line is configured to provide the d-th level first output clock signal, the c-th level second output clock signal line is configured to provide the c-th level second output clock signal, and the d-th level first output clock signal and the c-th level second output clock signal are reciprocal signals;
the c-th second control terminal is electrically connected to a d-th level first drive signal terminal comprised in the d-th first driver circuit;
values c and d are positive integers.
15. The driver module according to claim 14 , wherein the c-th second control circuit comprises a c-th second control transistor;
a gate of the c-th second control transistor is electrically connected to the d-th level first drive signal terminal, a first pole of the c-th second control transistor is electrically connected to the first terminal of the c-th row second gate line, and a second pole of the c-th second control transistor is electrically connected to the second voltage signal terminal.
16. A driver module, applied to a display device including M rows of first gate lines; the driver module comprising: a first driver unit and a first control unit; wherein the first driver unit comprises M levels of first driver circuits; an m-th level first driver circuit comprises an m-th level first drive signal output terminal; M is a positive integer; m is a positive integer less than or equal to M;
the m-th level first drive signal output terminal is electrically connected to a first terminal of an m-th row first gate line, and is configured to provide an m-th level first drive signal to the m-th row first gate line through the m-th level first drive signal output terminal;
the first control unit comprises M first control circuits;
an m-th first control circuit comprised in the first control unit is electrically connected to a second terminal of the m-th row first gate line, and configured to control the second terminal of the m-th row first gate line to receive an ineffective voltage signal when a voltage value of the m-th level first drive signal changes from an effective voltage to an ineffective voltage;
the first terminal and the second terminal are opposite terminals:
wherein the display device further comprises N rows of second gate lines; the driver module further comprises a second driver unit and a second control unit; the second driver unit comprises N levels of second driver circuits; an n-th level second driver circuit comprises an n-th level second drive signal output terminal; N is a positive integer; n is a positive integer less than or equal to N;
the n-th level second drive signal output terminal is electrically connected to a second terminal of an n-th row second gate line, and configured to provide an n-th level second drive signal to the n-th row second gate line through the n-th level second drive signal output terminal;
the second control unit comprises N second control circuits;
an n-th second control circuit comprised in the second control unit is electrically connected to a first terminal of the n-th row second gate line, and configured to control the first terminal of the n-th row second gate line to receive an ineffective voltage signal when a voltage value of the n-th level second drive signal changes from an effective voltage to an ineffective voltage;
wherein an a-th first control circuit comprised in the first control unit is configured to, under control of an a-th first control signal provided by an a-th first control terminal, control a connection between a second terminal of an a-th row first gate line and a first voltage signal terminal;
an a-th level first driver circuit comprised in the first driver unit is electrically connected to an a-th level first output clock signal line, and configured to, under control of a potential of an a-th level first pull-up node, control the a-th level first output clock signal line to provide an a-th level first output clock signal to an a-th level first drive signal output terminal;
an e-th level first driver circuit comprised in the first driver unit is electrically connected to an e-th level first output clock signal line, and configured to, under control of a potential of an e-th level first pull-up node, control the e-th level first output clock signal line to provide an e-th level first output clock signal to an e-th level first drive signal output terminal;
the a-th level first output clock signal line is configured to provide the a-th level first output clock signal, the e-th level first output clock signal line is configured to provide the e-th level first output clock signal, and the a-th level first output clock signal and the e-th level first output clock signal are reciprocal signals;
the a-th first control terminal is electrically connected to an e-th level first drive signal terminal comprised in the e-th level first driver circuit;
values a and e are positive integers.
17. The driver module according to claim 16 , wherein the a-th first control circuit comprises an a-th first control transistor;
a gate of the a-th first control transistor is electrically connected to the e-th level first drive signal terminal, a first pole of the a-th first control transistor is electrically connected to the second terminal of the a-th row first gate line, and a second pole of the a-th first control transistor is electrically connected to the first voltage signal terminal.
18. The driver module according to claim 16 , wherein a c-th second control circuit comprised in the second control unit is configured to, under control of a c-th second control signal provided by a c-th second control terminal, control a connection between a first terminal of a c-th row second gate line and a second voltage signal terminal;
a c-th level second driver circuit comprised in the second driver unit is electrically connected to a c-th level second output clock signal line, and configured to, under control of a potential of a c-th level second pull-up node, control the c-th level second output clock signal line to provide a c-th level second output clock signal to a c-th level second drive signal output terminal;
an f-th level second driver circuit comprised in the second driver unit is electrically connected to an f-th level second output clock signal line, and configured to, under control of a potential of an f-th level second pull-up node, control the f-th level second output clock signal line to provide an f-th level second output clock signal to an f-th level second drive signal output terminal;
the c-th level second output clock signal line is configured to provide the c-th level second output clock signal, the f-th level second output clock signal line is configured to provide the f-th level second output clock signal, and the c-th level second output clock signal and the f-th level second output clock signal are reciprocal signals;
the c-th second control terminal is electrically connected to an f-th level second drive signal terminal comprised in the f-th level second driver circuit;
values c and f are positive integers.
19. The driver module according to claim 18 , wherein
the c-th second control circuit comprises a c-th second control transistor;
a gate of the c-th second control transistor is electrically connected to the f-th level second drive signal terminal, a first pole of the c-th second control transistor is electrically connected to the first terminal of the c-th row second gate line, and a second pole of the c-th second control transistor is electrically connected to the second voltage signal terminal.