Synapse device and method of operating the same
A synapse device may include an oxide semiconductor transistor divided into a write transistor and a read transistor. The write transistor is an oxide semiconductor transistor having a dual gate including a bottom gate located below a thin oxide semiconductor layer and a top gate located above the thin oxide semiconductor layer.
1. A synapse device, comprising:
an oxide semiconductor transistor divided into a write transistor and a read transistor,
wherein the write transistor is an oxide semiconductor transistor including a dual gate comprising:
a bottom gate located below a thin oxide semiconductor layer; and
a top gate located above the thin oxide semiconductor layer.
2. The synapse device of claim 1 , wherein each of the top gate and the bottom gate of the oxide semiconductor transistor is adjustable in threshold voltage.
3. The synapse device of claim 1 , wherein the oxide semiconductor transistor comprises:
a semiconductor substrate;
a bottom gate formed over the semiconductor substrate;
a bottom gate insulator formed over the bottom gate;
a thin oxide semiconductor layer formed over the bottom gate insulator;
source and drain electrodes formed on both ends of the thin oxide semiconductor layer;
a top gate insulator formed over the thin oxide semiconductor layer; and
a top gate formed over the top gate insulator.
4. The synapse device of claim 1 , further comprising:
an ultra-thin insulator layer provided over the thin oxide semiconductor layer, wherein the ultra-thin insulator layer is formed of any one selected from SiO2, Al2O3, HfO2, a self-assembled monomolecular layer, and a combination thereof.
5. The synapse device of claim 1 , wherein programming is for being performed only when the top gate and the bottom gate of the write transistor are simultaneously activated.
6. A method of operating a synapse array using a synapse device comprising an oxide semiconductor transistor divided into a write transistor and a read transistor, wherein the write transistor is formed in a dual gate structure comprising: a bottom gate located below a thin oxide semiconductor layer; and a top gate located above the thin oxide semiconductor layer, and wherein the method comprises:
programming a selected cell by individually adjusting a threshold voltage of each of the bottom gate and the top gate.
7. The method of claim 6 , wherein a programming pulse is applied to the top gate, and a DC signal for selecting whether or not to program is applied to the bottom gate.
8. The method of claim 6 , wherein programming is possible only when the top gate and the bottom gate of the write transistor are simultaneously activated.
9. The method of claim 6 , wherein a write transistor of a corresponding cell is deactivated by increasing the threshold voltage of the write transistor of a cell different from the selected cell.
10. The method of claim 6 , wherein programming is performed only when an ON voltage is applied to the top gate and the bottom gate, so update time in total time is determined by a product of a duty ratio of a row and a column.
11. A method of operating a synapse array using a synapse device comprising an oxide semiconductor transistor divided into a write transistor and a read transistor, the method comprising:
controlling a threshold voltage through a select line connected to a selected cell;
activating a gate line connected to the selected cell; and
activating only the write transistor of the selected cell among cells connected to the gate line according to a control result of the threshold voltage, thus programming the selected cell.
12. The method of claim 11 , wherein the controlling the threshold voltage comprises controlling the threshold voltage by applying a specific voltage to a top gate of the write transistor through the select line.
13. The method of claim 12 , wherein the controlling the threshold voltage comprises causing a voltage greater than a voltage applied to the bottom gate of the write transistor to be applied to the top gate.