Extending functionality of memory controllers using a loopback mode for testing in a processor-based device
Apparatus and methods for extending functionality of memory controllers using a loopback mode for testing are disclosed herein. In one aspect, a processor-based device provides a memory access intercept circuit configured to receive a memory write request that is directed to and received by a memory controller. The memory access intercept circuit transmits proxy write data to the memory controller, and intercepts write data directed to the memory controller for the memory write request. The memory access intercept circuit stores the write data in a write data buffer, and, upon intercepting the proxy write data from the memory controller directed to a physical (PHY) interface circuit, retrieves the write data from the write data buffer and transmits the write data to the PHY interface circuit. The memory access intercept circuit subsequently receives, from the PHY interface circuit, loopback data, and stores the loopback data in a read data buffer.
1. A processor-based device, comprising:
a memory controller;
a physical (PHY) interface circuit communicatively coupled to the memory controller, wherein the PHY interface circuit is configured to operate in a loopback mode; and
a memory access intercept circuit configured to operate in the loopback mode by being configured to:
receive, from a requestor, a memory write request that is directed to and received by the memory controller;
transmit proxy write data to the memory controller;
intercept write data from the requestor directed to the memory controller for the memory write request;
store the write data in a write data buffer;
intercept the proxy write data from the memory controller directed to the PHY interface circuit;
retrieve the write data from the write data buffer;
transmit the write data to the PHY interface circuit;
receive, from the PHY interface circuit, loopback data directed to the memory controller in response to a read signal from the memory access intercept circuit; and
store the loopback data in a read data buffer.
2. The processor-based device of claim 1 , wherein:
the memory access intercept circuit is further configured to:
generate a write transaction identifier (ID) for the memory write request; and
generate a read transaction ID for the read signal; and
the memory access intercept circuit is configured to:
transmit the proxy write data to the memory controller by being configured to transmit the write transaction ID to the memory controller as the proxy write data;
store the write data in the write data buffer by being configured to store the write data in the write data buffer in association with the write transaction ID;
retrieve the write data from the write data buffer by being configured to retrieve the write data from the write data buffer based on the write transaction ID of the proxy write data; and
store the loopback data in the read data buffer by being configured to store the loopback data in the read data buffer in association with the read transaction ID.
3. The processor-based device of claim 2 , wherein the memory access intercept circuit is further configured to:
transmit the read transaction ID to the memory controller as proxy read data;
intercept the proxy read data from the memory controller directed to the requestor;
retrieve the loopback data from the read data buffer based on the read transaction ID of the proxy read data; and
transmit the loopback data to the requestor.
4. The processor-based device of claim 3 , wherein the requestor comprises a testing circuit configured to:
perform a comparison of the write data and the loopback data; and
generate a test result indication based on the comparison.
5. The processor-based device of claim 1 , wherein:
the memory access intercept circuit is further configured to perform a first data transformation on the write data to generate first transformed data; and
the memory access intercept circuit is configured to transmit the write data to the PHY interface circuit by being configured to transmit the first transformed data as the write data.
6. The processor-based device of claim 5 , wherein the memory access intercept circuit is configured to perform the first data transformation by being configured to encrypt the write data.
7. The processor-based device of claim 5 , wherein the memory access intercept circuit is configured to perform the first data transformation by being configured to encode a custom error correction code (ECC) based on the write data.
8. The processor-based device of claim 1 , wherein the memory access intercept circuit is configured to receive the loopback data by being configured to:
receive, from the PHY interface circuit, second transformed data; and
perform a second data transformation on the second transformed data to obtain the loopback data.
9. The processor-based device of claim 8 , wherein the memory access intercept circuit is configured to perform the second data transformation by being configured to decrypt the second transformed data.
10. The processor-based device of claim 8 , wherein the memory access intercept circuit is configured to perform the second data transformation by being configured to decode a custom error correction code (ECC).
11. A method for extending functionality of memory controllers using a loopback mode for testing in a processor-based device, comprising:
receiving, by a memory access intercept circuit of the processor-based device from a requestor, a memory write request that is directed to and received by a memory controller of the processor-based device;
transmitting, by the memory access intercept circuit, proxy write data to the memory controller;
intercepting, by the memory access intercept circuit, write data from the requestor directed to the memory controller for the memory write request;
storing, by the memory access intercept circuit, the write data in a write data buffer;
intercepting, by the memory access intercept circuit, the proxy write data from the memory controller directed to a physical (PHY) interface circuit of the processor-based device;
retrieving, by the memory access intercept circuit, the write data from the write data buffer;
transmitting, by the memory access intercept circuit, the write data to the PHY interface circuit;
receiving, by the memory access intercept circuit from the PHY interface circuit, loopback data directed to the memory controller in response to a read signal from the memory access intercept circuit; and
storing, by the memory access intercept circuit, the loopback data in a read data buffer.
12. The method of claim 11 , wherein:
the method further comprises:
generating, by the memory access intercept circuit, a write transaction identifier (ID) for the memory write request; and
generating, by the memory access intercept circuit, a read transaction ID for the read signal;
transmitting the proxy write data to the memory controller comprises transmitting the write transaction ID to the memory controller as the proxy write data;
storing the write data in the write data buffer comprises storing the write data in the write data buffer in association with the write transaction ID;
retrieving the write data from the write data buffer comprises retrieving the write data from the write data buffer based on the write transaction ID of the proxy write data; and
storing the loopback data in the read data buffer comprises storing the loopback data in the read data buffer in association with the read transaction ID.
13. The method of claim 12 , further comprising:
transmitting, by the memory access intercept circuit, the read transaction ID to the memory controller as proxy read data;
intercepting, by the memory access intercept circuit, the proxy read data from the memory controller directed to the requestor;
retrieving, by the memory access intercept circuit, the loopback data from the read data buffer based on the read transaction ID of the proxy read data; and
transmitting, by the memory access intercept circuit, the loopback data to the requestor.
14. The method of claim 13 , wherein:
the requestor comprises a testing circuit; and
the method further comprises:
performing, by the testing circuit, a comparison of the write data and the loopback data; and
generating, by the testing circuit, a test result indication based on the comparison.
15. The method of claim 11 , wherein:
the method further comprises performing, by the memory access intercept circuit, a first data transformation on the write data to generate first transformed data; and
transmitting the write data to the PHY interface circuit comprises transmitting the first transformed data as the write data.
16. The method of claim 15 , wherein performing the first data transformation comprises encrypting the write data.
17. The method of claim 15 , wherein performing the first data transformation comprises encoding a custom error correction code (ECC) based on the write data.
18. The method of claim 11 , wherein receiving the loopback data comprises:
receiving, from the PHY interface circuit, second transformed data; and
performing a second data transformation on the second transformed data to obtain the loopback data.
19. The method of claim 18 , wherein performing the second data transformation comprises decrypting the second transformed data.
20. The method of claim 18 , wherein performing the second data transformation comprises decoding a custom error correction code (ECC).