Semiconductor package
A semiconductor package includes a first package substrate, a semiconductor chip on the first package substrate, a second package substrate over the first package substrate and the semiconductor chip, and a plurality of core structures and a plurality of solder balls. The core structures and the solder balls are between the first package substrate and the second package substrate, a first portion of the plurality of core structures and the plurality of solder balls are apart from the semiconductor chip in a first dimension direction, and a second portion of the plurality of core structures and the plurality of solder balls are apart from the semiconductor chip in a second dimension direction that is different than the first dimension direction. The semiconductor package includes a plurality of strip guides between the semiconductor chip and the plurality of core structures, and in parallel with a periphery of the semiconductor chip.
1. A semiconductor package comprising:
a first package substrate;
a semiconductor chip on the first package substrate;
a second package substrate over the first package substrate and the semiconductor chip;
a plurality of core structures and a plurality of solder balls, the plurality of core structures and the plurality of solder balls between the first package substrate and the second package substrate, a first portion of the plurality of core structures and the plurality of solder balls being apart from the semiconductor chip in a first dimension direction, and a second portion of the plurality of core structures and the plurality of solder balls being apart from the semiconductor chip in a second dimension direction that is different than the first dimension direction; and
a plurality of strip guides between the semiconductor chip and the plurality of core structures, the plurality of strip guides in parallel with a periphery of the semiconductor chip.
2. The semiconductor package of claim 1 ,
wherein each of the plurality of core structures comprises a core layer, and a solder layer surrounding the core layer.
3. The semiconductor package of claim 2 ,
wherein the core layer comprises copper, and the solder layer comprises a conductive solder.
4. The semiconductor package of claim 1 ,
wherein each of the plurality of core structures has a rugby ball shape in which a horizontal width of the core structure is greater than a vertical height of the core structure.
5. The semiconductor package of claim 1 ,
wherein the plurality of core structures are in rows between two opposite edges of the first package substrate and two opposite edges of the semiconductor chip corresponding to the two opposite edges of the first package substrate.
6. The semiconductor package of claim 1 ,
wherein the plurality of core structures are in rows between four edges of the first package substrate and four edges of the semiconductor chip corresponding to the four edges of the first package substrate.
7. The semiconductor package of claim 1 ,
wherein the plurality of core structures are symmetrical with respect to a central portion of the semiconductor chip in both the first dimension direction and the second dimension direction.
8. The semiconductor package of claim 1 ,
wherein a vertical height of each of the plurality of strip guides is in a range of 0.5 times to 1 time a vertical height of the plurality of core structures.
9. The semiconductor package of claim 8 ,
wherein a vertical height of some of the plurality of strip guides is different from a vertical height of others of the plurality of strip guides.
10. The semiconductor package of claim 1 ,
wherein a cross-section of the plurality of strip guides that is vertical to an extension direction of the plurality of strip guides has a rectangular shape in which a vertical height of the cross-section is greater than a horizontal width of the cross-section.
11. The semiconductor package of claim 1 ,
wherein the plurality of strip guides are symmetrical with respect to a central portion of the semiconductor chip in both the first dimension direction and the second dimension direction.
12. The semiconductor package of claim 1 ,
wherein the plurality of strip guides comprise a plurality of first sub-strip guides and a plurality of second sub-strip guides,
wherein the plurality of first sub-strip guides are between two opposite edges of the first package substrate and two opposite edges of the semiconductor chip corresponding to the two opposite edges of the first package substrate, and
wherein the plurality of second sub-strip guides are between two other opposite edges of the first package substrate and two other opposite edges of the semiconductor chip.
13. The semiconductor package of claim 12 ,
wherein the plurality of first sub-strip guides extend in parallel with the two opposite edges of the first package substrate, and
the plurality of second sub-strip guides extend in parallel with the two other opposite edges of the first package substrate.
14. A semiconductor package comprising:
a lower package comprising:
a first package substrate;
a first semiconductor chip on the first package substrate;
a second package substrate over the first package substrate and the first semiconductor chip;
a plurality of core structures and a plurality of solder balls, the plurality of core structures and the plurality of solder balls between the first package substrate and the second package substrate, a first portion of the plurality of core structures and the plurality of solder balls being apart from the first semiconductor chip in a first dimension direction, and a second portion of the plurality of core structures and the plurality of solder balls being apart from the first semiconductor chip in a second dimension direction that is different than the first dimension direction; and
a plurality of strip guides between the first semiconductor chip and the plurality of solder balls, the plurality of strip guides between the first semiconductor chip and the plurality of core structures; and
an upper package comprising,
a third package substrate;
a second semiconductor chip on the third package substrate; and
a package connection member between the lower package and the upper package, and the package connection member electrically connects the lower package to the upper package.
15. The semiconductor package of claim 14 ,
wherein a space width between each of the plurality of strip guides is in a range from 220 μm to 300 μm.
16. The semiconductor package of claim 14
wherein a horizontal width of each of the plurality of strip guides is in a range from 20 μm to 40 μm.
17. The semiconductor package of claim 14 ,
wherein a cross-section of the plurality of strip guides, which is vertical to an extension direction of the plurality of strip guides, has a convex upper surface.
18. The semiconductor package of claim 14 ,
wherein the plurality of core structures and the plurality of strip guides are symmetrical with respect to a central portion of the first semiconductor chip in both the first dimension direction and the second dimension direction.
19. A semiconductor package comprising:
a first package substrate;
a semiconductor chip on the first package substrate;
a second package substrate over the first package substrate and the semiconductor chip;
a molding layer between the first package substrate and the second package substrate, and surrounding the semiconductor chip;
a plurality of core structures penetrating the molding layer, a first portion of the plurality of core structures being apart from the semiconductor chip in a first dimension direction, a second portion of the plurality of core structures being apart from the semiconductor chip in a second dimension direction that is different from the first dimension direction, and the plurality of core structures in symmetrical rows with respect to a central portion of the semiconductor chip;
a plurality of solder balls penetrating the molding layer, and connect the first package substrate to the second package substrate; and
a plurality of strip guides comprising a plurality of first sub-strip guides and a plurality of second sub-strip guides,
wherein the plurality of first sub-strip guides are between two opposite edges of the first package substrate and two opposite edges of the semiconductor chip corresponding to the two opposite edges of the first package substrate, and in parallel with the two opposite edges of the first package substrate, and a cross-section of the plurality of first sub-strip guides, which is vertical to an extension direction of the plurality of first sub-strip guides, has a rectangular shape in which a vertical height of the cross-section of the plurality of first sub-strip guides is greater than a horizontal width of the cross-section of the plurality of first sub-strip guides, and
wherein the plurality of second sub-strip guides are arranged between two other opposite edges of the first package substrate and two other opposite edges of the semiconductor chip, and in parallel with the two other opposite edges of the first package substrate, and a cross-section of the plurality of second sub-strip guides, which is vertical to an extension direction of the plurality of second sub-strip guides, has a rectangular shape in which a vertical height of the cross-section of the plurality of second sub-strip guides is greater than a horizontal width of the cross-section of the plurality of second sub-strip guides.
20. The semiconductor package of claim 19 ,
wherein the plurality of strip guides comprise copper.