IP Library Granted Patent US 12,451,631
Granted Patent B2
US 12,451,631 · App. 18/160,365 · Granted Oct 21, 2025

Interconnect substrate including substrates and connector disposed in recess

Inventor: Atsuto Yoda (Nagano, JP)
Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
H01R12/722H01R12/52H05K1/14H05K1/144H05K3/368H01L23/3128H01L23/49811H01L23/49816H01L23/49827H01L23/538H01L23/5385H01L23/5386H01L25/165H01R12/51H01R12/523H01R12/71H01R12/712H01R12/714H01R12/716H01R12/718H01R12/728H05K1/145H05K3/36H05K2201/04H05K2201/042H05K2201/095H05K2201/09545H05K2201/096H05K2201/10227H05K2201/10234H05K2201/10378H05K2201/10734
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Quick Facts
Patent No.
US 12,451,631
App. No.
18/160,365
Granted
Oct 21, 2025
Kind
B2
Abstract

An interconnect substrate includes a first interconnect substrate having a first electrode on a first surface and having a recess formed in an edge in a plan view normal to the first surface, a second interconnect substrate having a second electrode on a second surface facing toward the first surface, a connector disposed inside the recess and electrically connected to the first interconnect substrate, an intermediate substrate disposed between the first interconnect substrate and the second interconnect substrate, the intermediate substrate including an insulating base and a conductive via, the insulating base having a through hole extending from a third surface facing the first surface to a fourth surface facing the second surface, the conductive via being disposed in the through hole, a first conductive member electrically connecting the first electrode and the conductive via, and a second conductive member electrically connecting the second electrode and the conductive via.

Claims (19)

1. An interconnect substrate, comprising:

a first interconnect substrate having a first electrode on a first surface thereof and having a recess formed in an edge thereof in a plan view normal to the first surface;

a second interconnect substrate having a second electrode on a second surface thereof facing toward the first surface;

a connector disposed inside the recess and electrically connected to the first interconnect substrate;

an intermediate substrate disposed between the first interconnect substrate and the second interconnect substrate, the intermediate substrate including an insulating base and a conductive via, the insulating base having a through hole extending from a third surface thereof facing the first surface to a fourth surface thereof facing the second surface, the conductive via being disposed in the through hole;

a first conductive member electrically connecting the first electrode and the conductive via; and

a second conductive member electrically connecting the second electrode and the conductive via,

wherein the insulating base of the intermediate substrate does not overlap the connector in the plan view, and includes a first region and a second region, the first region extending in a predetermined direction in the plan view, the second region located opposite the first region across the recess in the plan view and extending in the predetermined direction in the plan view.

2. The interconnect substrate as claimed in claim 1 , wherein at least a part of the connector overlaps the second interconnect substrate in the plan view.

3. The interconnect substrate as claimed in claim 2 , wherein an entirety of the connector overlaps the second interconnect substrate in the plan view.

4. The interconnect substrate as claimed in claim 1 , further comprising:

a first electronic component mounted on a fifth surface of the first interconnect substrate opposite the first surface thereof; and

a second electronic component mounted on a sixth surface of the second interconnect substrate opposite the second surface thereof.

5. The interconnect substrate as claimed in claim 4 , wherein the second electronic component mounted on the sixth surface overlaps at least a portion of the connector in the plan view.

6. The interconnect substrate as claimed in claim 1 , comprising a plurality of said intermediate substrates.

7. The interconnect substrate as claimed in claim 1 , wherein the first conductive member includes a first conductive core ball, and the second conductive member includes a second conductive core ball.

8. The interconnect substrate as claimed in claim 7 , wherein the first conductive core ball and the second conductive core ball contain copper.

9. The interconnect substrate as claimed in claim 7 , wherein the first conductive member includes a first solder layer covering the first conductive core ball, and the second conductive member includes a second solder layer covering the second conductive core ball.

10. The interconnect substrate as claimed in claim 1 , wherein the insulating base of the intermediate substrate has a U-shaped planar shape.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2023
From: YODA, ATSUTO
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 062505/0932 →
Priority Claims (1)
JP 2022-015631 · Feb 3, 2022 · national
Continuity (1)
Related Publication 20230246362A1 · Aug 3, 2023
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