Protection of a domain of an integrated circuit against overvoltages
View Patent ↗In embodiments, an integrated circuit is provided that includes an input/output cell having a first signal terminal and a second signal terminal connected to a domain and capable of withstanding a maximum voltage greater than the power supply voltage. The input/output cell further includes an array of N diodes coupled in series between the second signal terminal and a cold power supply point. The array has an overall threshold voltage greater than the maximum voltage. The integrated circuit further includes a control circuit connected between the first signal terminal and the array of diodes. The control circuit is configured, in the presence of a second voltage on the first signal terminal greater than the maximum voltage, to automatically and autonomously short-circuit at least one of the diodes in the array to limit the voltage on the second signal terminal to a third voltage less than the maximum voltage.
1. An integrated circuit, comprising:
an input/output cell comprising:
a first signal terminal for receiving/transmitting a signal,
a third signal terminal coupled to a domain and configured to operate under a power supply voltage and capable of withstanding a maximum voltage greater than the power supply voltage, and
an array comprising N diodes coupled in series between the third signal terminal and a cold power supply point, N being an integer greater than 0, the array having an overall threshold voltage greater than the maximum voltage; and
a control circuit coupled between the first signal terminal and the array, the control circuit configured to, in a presence of a second voltage on the first signal terminal greater than the maximum voltage, automatically and autonomously short-circuit at least one diode in the array to limit a voltage on the third signal terminal to a third voltage less than the maximum voltage, the control circuit comprising:
a second resistor coupled between the first signal terminal and the third signal terminal,
a first transistor, a drain terminal of the first transistor coupled to a node of the array located between two consecutive diodes, a source terminal of the first transistor coupled to the cold power supply point,
a second transistor, a source terminal of the second transistor coupled to the second resistor, a gate terminal of the second transistor coupled to the third signal terminal, and a drain terminal of the second transistor coupled to the gate terminal of the first transistor.
2. The integrated circuit of claim 1 , wherein a value of N is chosen to limit current leaks between a second signal terminal and the cold power supply point below a threshold during operation of the domain.
3. The integrated circuit of claim 1 , wherein the control circuit further comprises a first resistor coupled between the second resistor and the first signal terminal, the source terminal of the second transistor coupled to a node common to the first resistor and the second resistor.
4. The integrated circuit of claim 3 , wherein the control circuit further comprises a third resistor and a fourth resistor, the third resistor coupled between the drain terminal of the second transistor and the fourth resistor, the gate terminal of the first transistor coupled to a node common to the third resistor and the fourth resistor.
5. The integrated circuit of claim 1 , wherein the input/output cell further comprises a capacitor coupled between the first signal terminal and the gate terminal of the first transistor.
6. The integrated circuit of claim 1 , wherein the second transistor is a P channel metal oxide semiconductor (PMOS) transistor, and wherein the first transistor is an N channel metal oxide semiconductor (NMOS) transistor.
7. The integrated circuit of claim 1 , wherein the array comprises four diodes and the overall threshold voltage is approximately 4.4 volts, and wherein the control circuit is configured to short-circuit two of the four diodes when the second voltage exceeds the maximum voltage.
8. A method, comprising:
having an integrated circuit comprising an input/output cell and a control circuit, the input/output cell comprising a first signal terminal and a third signal terminal coupled to a domain, the first signal terminal used to receive or transmit a signal, the third signal terminal operating under a power supply voltage and capable of withstanding a maximum voltage greater than the power supply voltage, the input/output cell further comprising an array comprising of N diodes coupled in series between the third signal terminal and a cold power supply point, N being an integer greater than 0, the array having an overall threshold voltage greater than the maximum voltage, the control circuit coupled between the first signal terminal and the array; and
automatically and autonomously short circuiting, by the control circuit, at least one diode in the array to limit a voltage on the third signal terminal to a third voltage less than the maximum voltage in a presence of a second voltage on the first signal terminal greater than the maximum voltage,
wherein the control circuit comprises:
a second resistor coupled between the first signal terminal and the third signal terminal,
a first transistor, a drain terminal of the first transistor coupled to a node of the array located between two consecutive diodes, a source terminal of the first transistor coupled to the cold power supply point,
a second transistor, a source terminal of the second transistor coupled to the second resistor, a gate terminal of the second transistor coupled to the third signal terminal, and a drain terminal of the second transistor coupled to the gate terminal of the first transistor.
9. The method of claim 8 , wherein a value of N is chosen to limit current leaks between the third signal terminal and the cold power supply point below a threshold during operation of the domain.
10. The method of claim 9 , wherein the control circuit further comprises a first resistor coupled between the second resistor and the first signal terminal, the source terminal of the second transistor coupled to a node common to the first resistor and the second resistor.
11. The method of claim 10 , wherein the control circuit further comprises a third resistor and a fourth resistor, the third resistor coupled between the drain terminal of the second transistor and the fourth resistor, the gate terminal of the first transistor coupled to a node common to the third resistor and the fourth resistor.
12. The method of claim 9 , wherein the input/output cell further comprises a capacitor coupled between the first signal terminal and the gate terminal of the first transistor.
13. The method of claim 9 , wherein the second transistor is a P channel metal oxide semiconductor (PMOS) transistor, and wherein the first transistor is an N channel metal oxide semiconductor (NMOS) transistor.
14. The method of claim 8 , wherein the array comprises four diodes and the overall threshold voltage is approximately 4.4 volts, and wherein the control circuit is configured to short-circuit two of the four diodes when the second voltage exceeds the maximum voltage.
15. An electronic device comprising an integrated circuit, the integrated circuit comprising:
an input/output cell comprising:
a first signal terminal for receiving/transmitting a signal,
a third signal terminal coupled to a domain and configured to operate under a power supply voltage and capable of withstanding a maximum voltage greater than the power supply voltage, and
an array comprising N diodes coupled in series between the third signal terminal and a cold power supply point, N being an integer greater than 0, the array having an overall threshold voltage greater than the maximum voltage; and
a control circuit coupled between the first signal terminal and the array, the control circuit configured to, in a presence of a second voltage on the first signal terminal greater than the maximum voltage, automatically and autonomously short-circuit at least one diode in the array to limit a voltage on the third signal terminal to a third voltage less than the maximum voltage,
wherein the control circuit comprises:
a second resistor coupled between the first signal terminal and the third signal terminal,
a first transistor, a drain terminal of the first transistor coupled to a node of the array located between two consecutive diodes, a source terminal of the first transistor coupled to the cold power supply point,
a second transistor, a source terminal of the second transistor coupled to the second resistor, a gate terminal of the second transistor coupled to the third signal terminal, and a drain terminal of the second transistor coupled to the gate terminal of the first transistor.
16. The electronic device of claim 15 , wherein a value of N is chosen to limit current leaks between the third signal terminal and the cold power supply point below a threshold during operation of the domain.
17. The electronic device of claim 15 , wherein the control circuit further comprises:
a first resistor coupled between the second resistor and the first signal terminal, a source terminal of the second transistor coupled to a node common to the first resistor and the second resistor;
a third resistor; and
a fourth resistor, the third resistor coupled between the drain terminal of the second transistor and the fourth resistor, the gate terminal of the first transistor coupled to a node common to the third resistor and the fourth resistor.
18. The electronic device of claim 15 , wherein the input/output cell further comprises a capacitor coupled between the first signal terminal and the gate terminal of the first transistor.
19. The electronic device of claim 15 , wherein the second transistor is a P channel metal oxide semiconductor (PMOS) transistor, and wherein the first transistor is an N channel metal oxide semiconductor (NMOS) transistor.
20. The electronic device of claim 15 , wherein the array comprises four diodes and the overall threshold voltage is approximately 4.4 volts, and wherein the control circuit is configured to short-circuit two of the four diodes when the second voltage exceeds the maximum voltage.