IP Library Granted Patent US 12,455,738
Granted Patent B2
US 12,455,738 · App. 17/134,251 · Granted Oct 28, 2025

Large-scale matrix restructuring and matrix-scalar operations

Inventors: Robert Pawlowski (Beaverton, OR); Ankit More (San Mateo, CA); Vincent Cave (Hillsboro, OR); Sriram Aananthakrishnan (Portland, OR); Jason M. Howard (Portland, OR); Joshua B. Fryman (Corvallis, OR)
Assignee: Intel Corporation
G06F9/30032G06F9/3001G06F9/30036G06F9/30038G06F9/3818G06F7/5443G06F17/16G06N3/08
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Quick Facts
Patent No.
US 12,455,738
App. No.
17/134,251
Granted
Oct 28, 2025
Kind
B2
Abstract

Embodiments of apparatuses and methods for copying and operating on matrix elements are described. In embodiments, an apparatus includes a hardware instruction decoder to decode a single instruction and execution circuitry, coupled to hardware instruction decoder, to perform one or more operations corresponding to the single instruction. The single instruction has a first operand to reference a base address of a first representation of a source matrix and a second operand to reference a base address of second representation of a destination matrix. The one or more operations include copying elements of the source matrix to corresponding locations in the destination matrix and filling empty elements of the destination matrix with a single value.

Claims (23)

1. An apparatus comprising:

a hardware instruction decoder to decode a single instruction having a first operand to reference a base address of a first representation of a source matrix, a second operand to reference a base address of second representation of a destination matrix, and a third operand to specify one of a plurality of fill values, wherein the plurality of fill values includes a zero and a one; and

execution circuitry to perform one or more operations corresponding to the single instruction, including:

copying elements of the source matrix to same element locations in the destination matrix; and

filling empty element locations of the destination matrix with the one of the plurality of fill values.

2. The apparatus of claim 1 , wherein the single instruction also has a fourth operand having a first field to specify a first number of rows of the source matrix.

3. The apparatus of claim 2 , wherein the fourth operand also has a second field to specify a second number of rows of the destination matrix.

4. The apparatus of claim 1 , wherein the single instruction also has a fourth operand having a first field to specify a first number of columns of the source matrix.

5. The apparatus of claim 4 , wherein the fourth operand also has a second field to specify a second number of columns of the destination matrix.

6. The apparatus of claim 1 , wherein the single instruction is also to specify a size of each element.

7. The apparatus of claim 1 , wherein the single instruction is also to specify an operation to perform on each element of the source matrix before copying to the destination matrix.

8. The apparatus of claim 7 , wherein the operation is to be performed on each element of the source matrix using a scalar value to be specified by the instruction.

9. A method comprising:

decoding, by a hardware instruction decoder, a single instruction having a first operand to reference a base address of a first representation of a source matrix, a second operand to reference a base address of second representation of a destination matrix, and a third operand to specify one of a plurality of fill values, wherein the plurality of fill values includes a zero and a one; and

performing, by execution circuitry, one or more operations corresponding to the single instruction, including:

copying elements of the source matrix to same element locations in the destination matrix; and

filling empty element locations of the destination matrix with the one of the plurality of fill values.

10. The method of claim 9 , wherein the single instruction also has a fourth operand having a first field to specify a first number of rows of the source matrix.

11. The method of claim 10 , wherein the fourth operand also has a second field to specify a second number of rows of the destination matrix.

12. The method of claim 9 , wherein the single instruction also has a fourth operand having a first field to specify a first number of columns of the source matrix.

13. The method of claim 12 , wherein the fourth operand also has a second field to specify a second number of columns of the destination matrix.

14. The method of claim 9 , wherein the single instruction is also to specify a size of each element.

15. The method of claim 9 , wherein the single instruction is also to specify an operation to perform on each element of the source matrix before copying to the destination matrix.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2021
From: PAWLOWSKI, ROBERT; MORE, ANKIT; CAVE, VINCENT; AANANTHAKRISHNAN, SRIRAM; HOWARD, JASON M.; FRYMAN, JOSHUA B.
To: INTEL CORPORATION
Reel/Frame 056171/0726 →
Continuity (2)
Provisional Application 63083912 · Sep 26, 2020
Related Publication 20220100508A1 · Mar 31, 2022
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