Computing device and operating method of computing device for mapping quantum circuit
View Patent ↗Disclosed is an operating method of a computing device including obtaining information of a quantum chip including qubit nodes, calculating first costs between qubit nodes of the quantum chip, which are adjacent to each other, based on the information of the quantum chip, and calculating second costs between the qubit nodes of the quantum chip based on the costs.
1. An operating method of a computing device, the method comprising:
obtaining information of a quantum chip including qubit nodes;
calculating first 2-qubit quantum gate execution costs between qubit nodes of the quantum chip, which are adjacent to each other, based on the information of the quantum chip;
calculating second 2-qubit quantum gate execution costs between the qubit nodes of the quantum chip based on the first 2-qubit quantum gate execution costs;
mapping qubits of quantum algorithm into the qubit nodes of the quantum chip; and
mapping candidate quantum circuits based on the second 2-qubit quantum gate execution costs,
wherein the mapping of the candidate quantum circuits includes:
generating a first candidate quantum circuit, and
wherein the generating of the first candidate quantum circuit includes:
generating a directed acyclic graph (DAG) of quantum gates of the quantum algorithm;
selecting a front layer of the DAG; and
adding a 1-qubit gate among quantum gates of the front layer to the first candidate quantum circuit.
2. The method of claim 1 , wherein the 2-qubit quantum gate execution costs include attenuation of fidelity or a movement time.
3. The method of claim 1 , wherein the calculating of the second 2-qubit quantum gate execution costs is based on Floyd-Warshall algorithm.
4. The method of claim 1 , wherein the second 2-qubit quantum gate execution costs include moving costs when the qubit nodes respectively moves to other qubit nodes.
5. The method of claim 1 , wherein the generating of the first candidate quantum circuit further includes:
removing the 1-qubit gate added to the first candidate quantum circuit from the DAG; and
adding a next quantum gate, which is dependent on the 1-qubit gate, to the front layer.
6. The method of claim 1 , wherein the generating of the first candidate quantum circuit further includes:
when qubit nodes corresponding to inputs of a 2-qubit quantum gate of the front layer are adjacent to each other and have a minimum 2-qubit quantum gate execution cost, adding the 2-qubit quantum gate to the first candidate quantum circuit.
7. The method of claim 1 , wherein the generating of the first candidate quantum circuit further includes:
when qubit nodes corresponding to inputs of a 2-qubit quantum gate of the front layer are adjacent to each other and do not have a minimum 2-qubit quantum gate execution cost, adding swap candidate gates associated with the qubit nodes corresponding to the inputs of the 2-qubit quantum gate of the front layer.
8. The method of claim 7 , wherein the associated swap candidate gates move a qubit of a first qubit node to other qubits adjacent to a second qubit node among the first qubit node and the second qubit node, which correspond to the inputs of the 2-qubit quantum gate of the front layer.
9. The method of claim 7 , wherein the generating of the first candidate quantum circuit further includes:
adding the 2-qubit quantum gate of the front layer and a swap gate in which the qubit nodes corresponding to the inputs of the 2-qubit quantum gate of the front layer are adjacent to each other and which has a minimum 2-qubit quantum gate execution cost, from among the associated swap candidate gates to the first candidate quantum circuit.
10. The method of claim 1 , wherein the generating of the first candidate quantum circuit further includes:
when qubit nodes corresponding to inputs of a 2-qubit quantum gate of the front layer are not adjacent to each other, adding swap candidate gates associated with the qubit nodes corresponding to the inputs of the 2-qubit quantum gate of the front layer.
11. An operating method of a computing device, the method comprising:
obtaining information of a quantum chip including qubit nodes;
calculating first 2-qubit quantum gate execution costs between qubit nodes of the quantum chip, which are adjacent to each other, based on the information of the quantum chip;
calculating second 2-qubit quantum gate execution costs between the qubit nodes of the quantum chip based on the first 2-qubit quantum gate execution costs;
mapping qubits of quantum algorithm into the qubit nodes of the quantum chip;
mapping candidate quantum circuits based on the second 2-qubit quantum gate execution costs;
measuring performances of the candidate quantum circuits; and
determining a candidate quantum circuit, which has the highest performance, from among the candidate quantum circuits as a quantum circuit.
12. The method of claim 11 , wherein the measuring of the performances of the candidate quantum circuits includes:
measuring a performance of a first candidate quantum circuit, and
wherein the measuring of the performance of the first candidate quantum circuit includes:
measuring attenuations of fidelity between inputs and outputs of the first candidate quantum circuit; and
selecting the greatest attenuation of the fidelity as a performance of the first candidate quantum circuit.
13. The method of claim 11 , wherein the measuring of the performances of the candidate quantum circuits includes:
measuring a performance of a first candidate quantum circuit, and
wherein the measuring of the performance of the first candidate quantum circuit includes:
measuring passages of time between inputs and outputs of the first candidate quantum circuit; and
selecting the longest passage of the time as a performance of the first candidate quantum circuit.
14. A computing device comprising:
a cost calculation unit configured to calculate 2-qubit quantum gate execution costs between qubit nodes based on information of a quantum chip including the qubit nodes; and
a circuit mapping unit configured to map a quantum circuit based on the 2-qubit quantum gate execution costs and a quantum algorithm,
wherein the 2-qubit quantum gate execution costs include attenuation of fidelity of a movement time when the qubit nodes respectively moves to other qubit nodes, and
wherein the circuit mapping unit is further configured to map qubits of the quantum algorithm into the qubit nodes, map candidate quantum circuits based on one of the 2-qubit quantum gate execution costs; and generate a first candidate quantum circuit by generating a directed acyclic graph (DAG) of quantum gates of the quantum algorithm and selecting a front layer of the DAG, and adding a 1-qubit gate among quantum gates of the front layer to the first candidate quantum circuit.
15. The computing device of claim 14 , wherein the circuit mapping unit changes mapping between qubits of the quantum algorithm and the qubit nodes, generates two or more candidate quantum circuits including the first candidate quantum circuit, and determines a candidate quantum circuit, which has the highest performance, from among the two or more candidate quantum circuits as the quantum circuit.
16. The computing device of claim 15 , wherein the circuit mapping unit adds swap gates to the candidate quantum circuits as the 1-qubit gate based on the 2-qubit quantum gate execution costs and maps the candidate quantum circuits such that the candidate quantum circuits are capable of being executed in the quantum chip.