Vertical semiconductor device and method for fabricating the same
A method for fabricating a semiconductor device includes preparing a substrate including a first region and a second region, forming a lower alternating stack on the substrate; etching the lower alternating stack to form a lower opening in the second region, forming an upper alternating stack on the lower opening and the lower alternating stack to form recess portion caused by filling the lower opening in the second region, forming a mask layer on the upper alternating stack using the recess portion as an alignment key, and etching the upper alternating stack by using the mask layer as a barrier to form a pattern in the first region.
1. A method for fabricating a vertical semiconductor device comprising:
preparing a substrate including a first region and a second region;
forming a lower alternating stack on the substrate;
etching the lower alternating stack to form a lower opening in the second region;
forming an upper alternating stack on the lower opening and the lower alternating stack to form a recess portion caused by filling the lower opening in the second region;
forming a mask layer on the upper alternating stack by using the recess portion as an alignment key; and
etching the upper alternating stack by using the mask layer as a barrier to form a pattern in the first region,
wherein cross section of the lower opening has square shape with rounded corners.
2. The method of claim 1 , wherein the etching of the lower alternating stack to form the lower opening in the second region comprises:
forming a mask material on the lower alternating stack;
patterning the mask material to form an alignment key opening corresponding to the lower opening in the mask material; and
etching the lower alternating stack using the mask material as an etch barrier to form the lower opening.
3. The method of claim 2 , wherein the lower opening is an opening in the lower alternating stack that extends through all layers of the lower alternating stack.
4. The method of claim 3 , wherein the lower opening is part of a pattern of openings that are spaced apart from one another in two dimensions.
5. The method of claim 3 , wherein the openings occupy about 10% of the surface area of the pattern of openings.
6. The method of claim 3 , wherein a width dimension of the openings is the same as a length dimension of the openings.
7. The method of claim 2 , wherein the lower opening is a line and space-shaped pattern, and the line shape of the line and space-shaped pattern includes a closed portion, and the space shape of the line and space-shaped pattern is divided into a plurality of sub-closed portions and a plurality of opened portions.
8. The method of claim 1 , wherein the mask material includes positive photoresist or negative photoresist.
9. The method of claim 1 , wherein etching the lower alternating stack comprises forming a lower hole in the first region while forming the lower opening in the second region.
10. The method of claim 9 , further comprising filling the lower hole with a lower pillar structure.
11. The method of claim 10 , wherein etching the upper alternating stack using the mask layer as the etch barrier comprises:
forming an upper hole that exposes a top surface of the lower pillar structure; and
forming an upper pillar structure that fills the upper hole.
12. The method of claim 1 , wherein forming the lower alternating stack on the substrate comprising:
forming the lower alternating stack by alternating stacking a plurality of first dielectric layers and a plurality of first sacrificial layers on the substrate.
13. The method of claim 1 , wherein forming the upper alternating stack on the lower opening and the lower alternating stack to form the recess portion caused by filling the lower opening in the second region comprising:
forming the upper alternating stack by alternating stacking a plurality of second dielectric layers and a plurality of second sacrificial layers.