Efficient integration of a first substrate without solder bumps with a second substrate having solder bumps
A method of forming a semiconductor structure having a first substrate capable of electrically and mechanically connecting to a second substrate includes providing a first substrate without a solder bump. A solder bump receiving metal is formed over a top interconnect metal of the first substrate. The solder bump receiving metal may include platinum, a platinum alloy, nickel, or a nickel alloy. A passivation layer is formed, wherein the passivation layer is not situated under any portion of the solder bump receiving metal. A window is formed exposing a portion of the solder bump receiving metal. The method may further include providing a second substrate with a second substrate solder bump. The second substrate solder bump may be mechanically and electrically connecting to the exposed portion of the solder bump receiving metal of the first substrate.
1. A method of forming a semiconductor structure, said method comprising:
providing a first substrate without a solder bump;
forming a solder bump receiving metal over a top interconnect metal of said first substrate, said solder bump receiving metal being selected from the group consisting of platinum, a platinum alloy, nickel, and a nickel alloy;
forming a passivation layer, wherein said passivation layer is not situated under any portion of said solder bump receiving metal;
forming a window exposing a portion of said solder bump receiving metal;
wherein after processing of said first substrate, said exposed portion of said solder bump receiving metal is capable to electrically and directly mechanically connect to a second substrate.
2. The method of claim 1 further comprising:
providing said second substrate with a second substrate solder bump;
directly mechanically and electrically connecting said second substrate solder bump to said solder bump receiving metal of said first substrate.
3. The method of claim 2 , wherein said second substrate solder bump is mechanically and electrically connected to an under-bump metallization (UBM) of said second substrate.
4. The method of claim 2 , wherein said second substrate solder bump comprises gold (Au) and/or silver (Ag).
5. The method of claim 1 , wherein said forming said solder bump receiving metal over said top interconnect metal of said first substrate comprises:
forming a solder bump receiving metal layer over a top interconnect metal layer;
substantially concurrently patterning said solder bump receiving metal layer and said top interconnect metal layer.
6. The method of claim 1 , wherein said solder bump receiving metal has a thickness of between approximately one hundred angstroms (100 Å) and one thousand angstroms (1,000 Å).
7. The method of claim 1 , wherein said passivation layer comprises an oxide layer and/or a nitride layer.
8. The method of claim 1 , wherein said passivation layer does not comprise polybenzoxazole (PBO), polyimide (PI), or benzocyclobutene (BCB).
9. A semiconductor structure including a first substrate capable of electrically and mechanically connecting to a second substrate, said semiconductor structure comprising:
said first substrate without a solder bump;
a solder bump receiving metal over a top interconnect metal of said first substrate, said solder bump receiving metal being selected from the group consisting of platinum, a platinum alloy, nickel, and a nickel alloy;
a window exposing a portion of said solder bump receiving metal;
said exposed portion of said solder bump receiving metal being capable to electrically and directly mechanically connect to said second substrate;
a passivation layer, wherein said passivation layer is not situated under any portion of said solder bump receiving metal.
10. The semiconductor structure of claim 9 , wherein said solder bump receiving metal and said top interconnect metal have approximately the same width.
11. The semiconductor structure of claim 9 , wherein said solder bump receiving metal has a thickness of between approximately one hundred angstroms (100 Å) and one thousand angstroms (1,000 Å).
12. The semiconductor structure of claim 9 , wherein said passivation layer comprises an oxide layer and/or a nitride layer.
13. The semiconductor structure of claim 9 , wherein said passivation layer does not comprise polybenzoxazole (PBO), polyimide (PI), or benzocyclobutene (BCB).
14. A semiconductor structure including a first substrate electrically and mechanically connected to a second substrate, said semiconductor structure comprising:
a solder bump receiving metal over a top interconnect metal of said first substrate;
a window exposing a portion of said solder bump receiving metal of said first substrate;
a passivation layer, wherein said passivation layer is not situated under any portion of said solder bump receiving metal;
a second substrate solder bump directly mechanically and electrically connected to said exposed portion of said solder bump receiving metal of said first substrate.
15. The semiconductor structure of claim 14 , wherein said second substrate solder bump is mechanically and electrically connected to an under-bump metallization (UBM) of said second substrate.
16. The semiconductor structure of claim 14 , wherein said second substrate solder bump comprises gold (Au) and/or silver (Ag).
17. The semiconductor structure of claim 14 , wherein said solder bump receiving metal and said top interconnect metal have approximately the same width.
18. The semiconductor structure of claim 14 , wherein said solder bump receiving metal has a thickness of between approximately one hundred angstroms (100 Å) and one thousand angstroms (1,000 Å).
19. The semiconductor structure of claim 14 , wherein said passivation layer comprises an oxide layer and/or a nitride layer.
20. The semiconductor structure of claim 14 , wherein said passivation layer does not comprise polybenzoxazole (PBO), polyimide (PI), or benzocyclobutene (BCB).