Data detection on serial communication links
A serial data receiver subsystem of a computer system includes a data rate detection circuit and a receiver circuit. The data rate detection circuit is configured to detect that a communication link operates in a high-speed mode rather than in a low-speed mode by detecting that a number of transitions in a serial data stream over a reference period of time exceeds a threshold value. The date rate detection circuit is further configured to activate a data rate detection signal indicating that the communication link operates in the high-speed mode, the data rate detection signal activated in response to detection that the number of transitions in the serial data stream over the reference period of time exceeds the threshold value. The receiver circuit is configured to activate one or more of a plurality of subcircuits included in the receiver circuit in response to activation of the data rate detection signal.
1. An apparatus, comprising:
a data rate detection circuit configured to:
detect that a communication link operates in a high-speed mode rather than in a low-speed mode, wherein, to detect that the communication link operates in the high-speed mode, the data rate detection circuit is configured to determine that a number of samples sampled during a reference time period satisfy a threshold value, the samples generated based on a signal that encodes a serial data stream and received on the communication link; and
activate a data rate detection signal indicating that the communication link operates in the high-speed mode, wherein the data rate detection signal is activated in response to a determination that the number of samples satisfy the threshold value; and
a receiver circuit that includes a plurality of subcircuits, wherein the receiver circuit is configured to;
generate the samples during the reference time period, the samples generated based on the signal; and
activate one or more of the plurality of subcircuits in response to activation of the data rate detection signal.
2. The apparatus of claim 1 , further comprising:
a data detection circuit configured to detect the serial data stream on the communication link, wherein, to detect the serial data stream, the data detection circuit is configured to:
perform a comparison of a magnitude of the signal to a reference voltage, wherein the serial data stream includes a plurality of data symbols; and
activate a signal present indicator based on a result of the comparison.
3. The apparatus of claim 1 , wherein to generate the samples, the receiver circuit is configured to:
sample the signal using a first edge of a clock signal to generate a first sample; and
sample the signal using a second edge of the clock signal to generate a second sample.
4. The apparatus of claim 2 , wherein the data rate detection circuit is further configured to generate an enable signal, and wherein, to generate the enable signal, the data rate detection circuit is configured to filter the signal present indicator.
5. The apparatus of claim 1 , wherein the data rate detection circuit is further configured to adjust a value of the reference time period based on one or more operational characteristics of a computer system that includes the receiver circuit.
6. A method, comprising:
detecting, by a data rate detection circuit, that a communication link operates in a high-speed mode rather than in a low-speed mode, wherein the detecting includes determining that a number of samples sampled during a reference time period satisfy a threshold value, the samples generated based on a signal that encodes a serial data stream and received on the communication link;
activating, by the data rate detection circuit, a data rate detection signal indicating that the communication link operates in the high-speed mode, wherein the data rate detection signal is activated in response to a determination that the number of samples satisfy the threshold value; and
generating, by a receiver circuit that includes a plurality of subcircuits, the samples during the reference time period, the samples generated based on the signal; and
activating, by the receiver circuit, one or more of the plurality of subcircuits in response to activation of the data rate detection signal.
7. The method of claim 6 , further comprising:
detecting, by the data rate detection circuit, the serial data stream on the communication link, wherein detecting the serial data stream includes:
performing a comparison of a magnitude of the signal to a reference voltage, wherein the serial data stream that includes a plurality of data symbols; and
activating a signal present indicator based on a result of the comparison.
8. The method of claim 7 , further comprising:
generating, by the data rate detection circuit, an enable signal, wherein generating the enable signal includes filtering the signal present indicator.
9. The method of claim 6 , wherein generating the samples includes:
sampling the signal using a first edge of a clock signal to generate a first sample; and
sampling the signal using a second edge of the clock signal to generate a second sample.
10. The method of claim 6 , further comprising:
comparing, by the data rate detection circuit, the number of samples to the threshold value.
11. The method of claim 6 , further comprising:
adjusting, by the data rate detection circuit, a value of the reference time period based on one or more operational characteristics of a computer system that includes the receiver circuit.
12. An apparatus, comprising:
a first device configured to transmit at least one signal via a communication bus, wherein the at least one signal encodes a serial data stream that includes a plurality of data symbols; and
a second device coupled to the communication bus, wherein the second device includes:
a data rate detection circuit configured to:
detect that the communication bus operates in a high-speed mode rather than in a low-speed mode, wherein, to detect that the communication bus operates in the high-speed mode, the data rate detection circuit is configured to determine that a number of samples sampled during a reference time period satisfy a threshold value, the samples generated based on the signal; and
activate a data rate detection signal indicating that the communication bus operates in the high-speed mode, wherein the data rate detection signal is activated in response to a determination that the number of samples satisfy the threshold value; and
a receiver circuit including a plurality of subcircuits, wherein the receiver circuit is configured to:
generate the samples during the reference time period, the samples generated based on the signal; and
activate one or more of the plurality of subcircuits in response to activation of the data rate detection signal.
13. The apparatus of claim 12 , wherein the second device further includes:
a data detection circuit configured to detect the serial data stream on the communication bus, wherein, to detect the serial data stream, the data detection circuit is configured to:
perform a comparison of a magnitude of the signal to a reference voltage; and
activate a signal present indicator based on a result of the comparison.
14. The apparatus of claim 12 , wherein to generate the samples, the receiver circuit is configured to:
sample the signal using a first edge of a clock signal to generate a first sample; and
sample the signal using a second edge of the clock signal to generate a second sample.
15. The apparatus of claim 14 , wherein the receiver circuit is further configured to compare the first sample to the second sample.
16. The apparatus of claim 12 , wherein the data rate detection circuit is further configured to adjust a value of the reference time period based on one or more operational characteristics of a computer system that includes the first device and the second device.
17. The apparatus of claim 12 , further comprising:
the communication bus, wherein the communication bus is configured to couple the first device to the second device.
18. The apparatus of claim 1 , wherein the receiver circuit is further configured to process the samples to generate recovered data symbols.
19. The method of claim 6 , further comprising processing, by the receiver circuit, the samples to generate recovered data symbols.
20. The apparatus of claim 12 , wherein the receiver circuit is further configured to process the samples to generate recovered data symbols.