Voltage supply switch interlock logic
Circuits and methods that enable a “break-before-make” process for an electronic switch that avoids the relatively large time delays of fixed time delay circuitry. Logic gates, rather than a time delay, are used to lock out an input switch through-path from turning ON before another input switch through-path is fully turned OFF. An embodiment includes a first and second monitor logic blocks, configured such that (1) a first through-path is turned OFF before a first shunt-path is allowed to turn ON and before a second shunt-path is allowed to turn OFF, and the second shunt-path is turned OFF before a second through-path is allowed to turn ON; and (2) the second through-path is turned OFF before the second shunt-path is allowed to turn ON and before the first shunt-path is allowed to turn OFF, and the first shunt-path is turned OFF before the first through-path is allowed to turn ON.
1. An electronic switch, including:
(a) a first through-path coupled between a first input terminal and an output terminal, and a first shunt-path coupled between the first through-path and a reference potential;
(b) a second through-path coupled between a second input terminal and the output terminal, and a second shunt-path coupled between the second through-path and a reference potential;
(c) a first monitor logic block coupled to respective control inputs of the first through-path, the first shunt-path, and the second shunt path, the first monitor logic block responsive to a first combination of a first control signal and a second control signal;
(d) a second monitor logic block coupled to respective control inputs of the second through-path, the second shunt-path, and the first shunt path, the second monitor logic block responsive to a second combination of the first control signal and the second control signal;
wherein the first monitor logic block and the second monitor logic block are configured such that the first through-path is turned OFF before the first shunt-path is allowed to turn ON and before the second shunt-path is allowed to turn OFF, and the second shunt-path is turned OFF before the second through-path is allowed to turn ON; and
wherein the first monitor logic block and the second monitor logic block are configured such that the second through-path is turned OFF before the second shunt-path is allowed to turn ON and before the first shunt-path is allowed to turn OFF, and the first shunt-path is turned OFF before the first through-path is allowed to turn ON.
2. The electronic switch of claim 1 , wherein the first through-path and the second through-path each include a first NFET coupled in series to a second NFET.
3. The electronic switch of claim 2 , wherein the first shunt-path and the second shunt-path each include an NFET coupled to a node between the first and second NFETs, and configured to be coupled to a reference potential.
4. The electronic switch of claim 1 , further including an enable block configured to enable the first and second monitor logic blocks to enable the first through-path and the second shunt-path and disable the second through-path and the first shunt-path in response to receipt of the first combination of the first control signal and the second control signal, and to enable the second through-path and the first shunt-path and disable the first through-path and the second shunt-path in response to receipt of the second combination of the first control signal and the second control signal.
5. The electronic switch of claim 1 , wherein the first monitor logic block is coupled to a control input of the first shunt-path through a first inverter circuit including a PFET and an NFET coupled in series between a voltage supply and a reference potential, and the second monitor logic block is coupled to a control input of the second shunt-path through a second inverter circuit including a PFET and an NFET coupled in series between a voltage supply and a reference potential, wherein each PFET is sized to slowly turn ON the corresponding shunt-path.
6. An electronic switch, including:
(a) a first input terminal;
(b) a second input terminal;
(c) an output terminal;
(d) a first circuit block including a first through-path coupled between the first input terminal and the output terminal, and a first shunt-path coupled between the first through-path and a reference potential;
(e) a second circuit block including a second through-path coupled between the second input terminal and the output terminal, and a second shunt-path coupled between the second through-path and a reference potential;
(f) an enable block configured to receive a first control signal input and a second control signal input;
(g) a first monitor logic block coupled between the enable block and the first circuit block; and
(h) a second monitor logic block coupled between the enable block and the second circuit block;
wherein the first and second monitor logic blocks each have a cross-coupled connection to the other monitor logic block;
wherein the first monitor logic block and the second monitor logic block are configured such that the first through-path cannot turn ON to conduct a signal until the second through-path is OFF and the first shunt-path is OFF; and
wherein the first monitor logic block and the second monitor logic block are configured such that the second through-path cannot turn ON to conduct a signal until the first through-path is OFF and the second shunt-path is OFF.
7. The electronic switch of claim 6 , wherein the first through-path and the second through-path each include a first NFET coupled in series to a second NFET.
8. The electronic switch of claim 7 , wherein the first shunt-path and the second shunt-path each include an NFET coupled to a node between the first and second NFETs, and configured to be coupled to a reference potential.
9. The electronic switch of claim 6 , wherein the enable block is configured to enable the first and second monitor logic blocks to enable the first through-path and the second shunt-path and disable the second through-path and the first shunt-path in response to receipt of the first combination of the first control signal and the second control signal, and to enable the second through-path and the first shunt-path and disable the first through-path and the second shunt-path in response to receipt of the second combination of the first control signal and the second control signal.
10. The electronic switch of claim 6 , wherein the first monitor logic block is coupled to a control input of the first shunt-path through a first inverter circuit including a PFET and an NFET coupled in series between a voltage supply and a reference potential, and the second monitor logic block is coupled to a control input of the second shunt-path through a second inverter circuit including a PFET and an NFET coupled in series between a voltage supply and a reference potential, wherein each PFET is sized to slowly turn ON the corresponding shunt-path.
11. An electronic switch, including:
(a) a first input terminal;
(b) a second input terminal;
(c) an output terminal;
(d) a first circuit block including a first through-path coupled between the first input terminal and the output terminal, and a first shunt-path coupled between the first through-path and a reference potential;
(e) a second circuit block including a second through-path coupled between the second input terminal and the output terminal, and a second shunt-path coupled between the second through-path and a reference potential;
(f) an enable block configured to receive a first control signal input and a second control signal input;
(g) a first monitor logic block coupled between the enable block and the first circuit block; and
(h) a second monitor logic block coupled between the enable block and the second circuit block;
wherein the first and second monitor logic blocks each have a cross-coupled connection to the other monitor logic block;
wherein the first monitor logic block and the second monitor logic block are configured such that the first through-path is turned OFF before the first shunt-path is allowed to turn ON and before the second shunt-path is allowed to turn OFF, and the second shunt-path is turned OFF before the second through-path is allowed to turn ON; and
wherein the first monitor logic block and the second monitor logic block are configured such that the second through-path is turned OFF before the second shunt-path is allowed to turn ON and before the first shunt-path is allowed to turn OFF, and the first shunt-path is turned OFF before the first through-path is allowed to turn ON.
12. The electronic switch of claim 11 , wherein the first through-path and the second through-path each include a first NFET coupled in series to a second NFET.
13. The electronic switch of claim 12 , wherein the first shunt-path and the second shunt-path each include an NFET coupled to a node between the first and second NFETs, and configured to be coupled to a reference potential.
14. The electronic switch of claim 11 , wherein the enable block is configured to enable the first and second monitor logic blocks to enable the first through-path and the second shunt-path and disable the second through-path and the first shunt-path in response to receipt of the first combination of the first control signal and the second control signal, and to enable the second through-path and the first shunt-path and disable the first through-path and the second shunt-path in response to receipt of the second combination of the first control signal and the second control signal.
15. The electronic switch of claim 11 , wherein the first monitor logic block is coupled to a control input of the first shunt-path through a first inverter circuit including a PFET and an NFET coupled in series between a voltage supply and a reference potential, and the second monitor logic block is coupled to a control input of the second shunt-path through a second inverter circuit including a PFET and an NFET coupled in series between a voltage supply and a reference potential, wherein each PFET is sized to slowly turn ON the corresponding shunt-path.