On-die power supply monitor design
A system and method for efficiently measuring on-die power supply voltage are described. In various implementations, an integrated circuit includes power supply monitors across a die of the integrated circuit. A power supply monitor receives a power supply voltage and generates a code indicating a value of the power supply voltage. A first ring oscillator receives the power supply voltage and a pulse used as an enable signal. A pulse generator of the power supply monitor takes into account the process, voltage and temperature (PVT) characteristics of the integrated circuit by including at least a second ring oscillator and a modulus counter that receives an output of the second ring oscillator. Therefore, the pulse generated by the pulse generator is PVT dependent and increases gain of the power supply monitor.
1 . A power supply monitor circuit comprising:
a first ring oscillator configured to:
receive a pulse and a power supply voltage; and
generate, based on the power supply voltage, an output comprising a plurality of cycles responsive to determining the pulse has ended;
conversion circuitry configured to convert the output comprising the plurality of cycles to a value indicating a measure of the power supply voltage; and
a pulse generator comprising a second ring oscillator, wherein the second ring oscillator is configured to generate the pulse with a pulse width duration that is dependent on one or more of process, voltage, or temperature.
2 . The power supply monitor circuit as recited in claim 1 , wherein one or more stages of a plurality of stages of the second ring oscillator comprise a stack of serially connected p-type devices and a stack of serially connected n-type devices.
3 . The power supply monitor circuit as recited in claim 1 , wherein each of the pulse generator, and a plurality of storage elements that store the value, receive a clock signal with a fixed period causing a duration of the output of the first ring oscillator to be generated during a period of time that is dependent on one or more of process, voltage, or temperature.
4 . The power supply monitor circuit as recited in claim 2 , wherein a larger fanout of devices in the stack of serially connected devices reduces a gain of the power supply monitor circuit.
5 . The power supply monitor circuit as recited in claim 1 , wherein the pulse generator further comprises a modulus counter configured to receive an output of the second ring oscillator as an input clock, wherein the pulse generator is configured to end the pulse responsive to determining the modulus counter has reached its last state.
6 . The power supply monitor circuit as recited in claim 5 , wherein a larger size of the modulus counter increases a gain of the power supply monitor circuit.
7 . The power supply monitor circuit as recited in claim 5 , wherein the pulse generator further comprises a pulse flip-flop configured to:
receive the output of the second ring oscillator as an input clock; and
convey the pulse to the first ring oscillator.
8 . A method comprising:
receiving, by a first ring oscillator of a power supply monitor circuit, a pulse and a power supply voltage;
generating, based on the power supply voltage by the first ring oscillator, an output comprising a plurality of cycles responsive to determining the pulse has ended;
converting, by conversion circuitry of the power supply monitor circuit, the output comprising the plurality of cycles to a value indicating a measure of the power supply voltage; and
generating the pulse by a second ring oscillator of a pulse generator of the power supply monitor circuit with a pulse width duration that is dependent on one or more of process, voltage, or temperature.
9 . The method as recited in claim 8 , wherein one or more stages of a plurality of stages of the second ring oscillator comprise a stack of serially connected p-type devices and a stack of serially connected n-type devices.
10 . The method as recited in claim 8 , wherein each of the pulse generator, and a plurality of storage elements that store the value, receive a clock signal with a fixed period causing a duration of the output of the first ring oscillator to be generated during a period of time that is dependent on one or more of process, voltage, or temperature.
11 . The method as recited in claim 9 , wherein a larger fanout of devices in the stack of serially connected devices reduces a gain of the power supply monitor circuit.
12 . The method as recited in claim 8 , further comprising:
receiving, by a modulus counter of the pulse generator, an output of the second ring oscillator as an input clock; and
ending the pulse, by the pulse generator, responsive to determining the modulus counter has reached its last state.
13 . The method as recited in claim 12 , wherein a larger size of the modulus counter increases a gain of the power supply monitor circuit.
14 . The method as recited in claim 12 , further comprising:
receiving, by a pulse flip-flop, the output of the second ring oscillator as an input clock; and
conveying, by the pulse flip-flop, the pulse to the first ring oscillator.
15 . A computing system comprising:
a memory configured to store instructions of one or more tasks and source data to be processed by the one or more tasks;
an integrated circuit configured to execute the instructions using the source data, wherein the integrated circuit comprises one or more power supply monitor circuits, each comprising:
a first ring oscillator configured to:
receive a pulse and a power supply voltage; and
generate, based on the power supply voltage, an output comprising a plurality of cycles responsive to determining the pulse has ended;
conversion circuitry configured to convert the output comprising the plurality of cycles to a value indicating a measure of the power supply voltage; and
a pulse generator comprising a second ring oscillator, wherein the second ring oscillator is configured to generate the pulse with a pulse width duration that is dependent on one or more of process, voltage, or temperature.
16 . The computing system as recited in claim 15 , wherein one or more stages of a plurality of stages of the second ring oscillator comprise a stack of serially connected p-type devices and a stack of serially connected n-type devices.
17 . The computing system as recited in claim 16 , wherein a larger number of devices in the stack of serially connected devices reduces a gain of the one or more power supply monitor circuits.
18 . The computing system as recited in claim 15 , wherein each of the pulse generator, and a plurality of storage elements that store the value, receive a clock signal with a fixed period causing a duration of the output of the first ring oscillator to be generated during a period of time that is dependent on one or more of process, voltage, or temperature.
19 . The computing system as recited in claim 15 , wherein the pulse generator further comprises a modulus counter configured to receive an output of the second ring oscillator as an input clock, wherein the pulse generator is configured to end the pulse responsive to determining the modulus counter has reached its last state.
20 . The computing system as recited in claim 19 , wherein a larger size of the modulus counter increases a gain of the one or more power supply monitor circuits.