IP Library › Granted Patent US 12,461,661
Granted Patent B2
US 12,461,661 · App. 18/624,657 · Granted Nov 4, 2025

Dynamic block categorization to improve reliability and performance in memory sub-system

Inventors: Sandeep Reddy Kadasani (Meridian, ID); Pitamber Shukla (San Jose, CA); Scott Anthony Stoller (Boise, ID); Niccolo' Righetti (Boise, ID)
Assignee: Micron Technology, Inc.
G06F3/0619G06F3/064G06F3/0653G06F3/0688
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,461,661
App. No.
18/624,657
Granted
Nov 4, 2025
Kind
B2
Abstract

A set of threshold voltage distribution width measurements are obtained for a block in a memory device. An endurance estimate is determined for the block based on the threshold voltage distribution width measurements. The endurance estimate comprises an indication of an estimated number of program/erase cycles during which data can be reliably stored by the block. One or more parameters of the block are managed based on the endurance estimate.

Claims (54)

1 . A system comprising:

a memory device comprising a set of blocks; and

a processing device coupled to the memory device, the processing device configured to perform operations comprising:

obtaining a set of threshold voltage distribution width measurements for a block in the set of blocks;

assigning the block to a group among multiple groups of blocks based on the set of threshold voltage distribution width measurements;

determining an endurance estimate for the block based on an endurance category assigned to the group, the determining of the endurance estimate comprising determining an estimated number of program/erase cycles during which the block is able to store data reliably based on the endurance category; and

managing one or more parameters of the block based on the endurance estimate.

2 . The system of claim 1 , wherein the operations comprise:

determining a range of threshold voltage distribution width degradation rates among the set of blocks; and

dividing the range into multiple sub-ranges, where the assigning of the block to the group is based on the threshold voltage distribution width degradation rate for the block corresponding to a sub-range associated with group.

3 . The system of claim 1 , wherein the managing of the one or more parameters of the block comprises maintaining the block in a static single level cell pool for a number of program/erase cycles based on the endurance estimate.

4 . The system of claim 1 , wherein the determining of the endurance estimate for the block comprises accessing look-up table to identify the endurance estimate for the endurance category.

5 . The system of claim 1 , wherein the operations comprise assigning the group to the endurance category, the endurance category being associated with the endurance estimate.

6 . The system of claim 1 , wherein the obtaining of the set of threshold voltage distribution width measurements comprises:

measuring a first threshold voltage distribution width for the block based on a first number of program/erase cycles being performed on the block; and

measuring a second threshold voltage distribution width for the block based on a second number of program/erase cycles being performed on the block.

7 . The system of claim 6 , wherein the measuring of the first threshold voltage distribution width comprises:

determining a top edge and bottom edge of a threshold voltage distribution of the block; and

determining a difference between the top edge and the bottom edge of the threshold voltage distribution.

8 . The system of claim 1 , wherein the managing of the one or more parameters comprises:

assigning a program/erase cycle threshold to the block based on the estimated endurance, the program/erase cycle threshold defining a maximum number of program/erase cycles to be performed on the block;

determining the maximum number of program/erase cycles have been performed on the block; and

based on the determining the maximum number of program/erase cycles have been performed, retiring the block.

9 . The system of claim 1 , wherein the managing of the one or more parameters comprises dynamically adjusting wear-leveling on the block based on the endurance estimate.

10 . A method comprising:

obtaining a set of threshold voltage distribution width measurements for a block in a memory device;

assigning the block to a group among multiple groups of blocks based on the set of threshold voltage distribution width measurements;

determining, by a processing device, an endurance estimate for the block based on an endurance category assigned to the group, the determining of the endurance estimate comprising determining an estimated number of program/erase cycles during which the block is able to store data reliably based on the endurance category; and

managing one or more parameters of the block based on the endurance estimate.

11 . The method of claim 10 , comprising:

determining a range of threshold voltage distribution width degradation rates among the set of blocks; and

dividing the range into multiple sub-ranges, where the assigning of the block to the group is based on the threshold voltage distribution width degradation rate for the block corresponding to a sub-range associated with group.

12 . The method of claim 10 , wherein the managing of the one or more parameters of the block comprises maintaining the block in a static single level cell pool for a number of program/erase cycles based on the endurance estimate.

13 . The method of claim 10 , wherein the determining of the endurance estimate for the block comprises accessing look-up table to identify the endurance estimate for the endurance category.

14 . The method of claim 10 , comprising assigning the group to the endurance category, the endurance category being associated with the endurance estimate.

15 . The method of claim 10 , wherein the obtaining of the set of threshold voltage distribution width measurements comprises:

measuring a first threshold voltage distribution width for the block based on a first number of program/erase cycles being performed on the block; and

measuring a second threshold voltage distribution width for the block based on a second number of program/erase cycles being performed on the block.

16 . The method of claim 15 , wherein the measuring of the first threshold voltage distribution width comprises:

determining a top edge and bottom edge of a threshold voltage distribution of the block; and

determining a difference between the top edge and the bottom edge of the threshold voltage distribution.

17 . The method of claim 10 , wherein the managing of the one or more parameters comprises:

assigning a program/erase cycle threshold to the block based on the estimated endurance, the program/erase cycle threshold defining a maximum number of program/erase cycles to be performed on the block;

determining the maximum number of program/erase cycles have been performed on the block; and

based on the determining the maximum number of program/erase cycles have been performed, retiring the block.

18 . The method of claim 10 , wherein the managing of the one or more parameters comprises dynamically adjusting wear-leveling on the block based on the endurance estimate.

19 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising:

obtaining a set of threshold voltage distribution width measurements for a block in the set of blocks;

assigning the block to a group among multiple groups of blocks based on the set of threshold voltage distribution width measurements;

determining an endurance estimate for the block based on an endurance category assigned to the group, the determining of the endurance estimate comprising determining an estimated number of program/erase cycles during which the block is able to store data reliably based on the endurance category; and

managing one or more parameters of the block based on the endurance estimate.

20 . A non-transitory computer-readable storage medium of claim 19 , wherein operations comprise:

determining a range of threshold voltage distribution width degradation rates among the set of blocks; and

dividing the range into multiple sub-ranges, where the assigning of the block to the group is based on the threshold voltage distribution width degradation rate for the block corresponding to a sub-range associated with group.

Continuity (2)
Continuation 17867204 · Jul 18, 2022
Related Publication 20240248616A1 · Jul 25, 2024
References Cited (29)
US 5608672A · Tang et al. · 1997 [cited by applicant]
US 6285588B1 · Fastow · 2001 [cited by applicant]
US 6429081B1 · Doong et al. · 2002 [cited by applicant]
US 6606273B1 · Guo et al. · 2003 [cited by applicant]
US 9047955B2 · Cometti et al. · 2015 [cited by applicant]
US 9195586B2 · Cometti et al. · 2015 [cited by applicant]
US 9224456B2 · Cometti et al. · 2015 [cited by applicant]
US 9377962B2 · Cometti et al. · 2016 [cited by applicant]
US 9449702B1 · Pinkovich et al. · 2016 [cited by applicant]
US 9954558B1 · Steiner et al. · 2018 [cited by applicant]
US 10373693B2 · Cha et al. · 2019 [cited by applicant]
US 11972114B2 · Kadasani · 2024 [cited by examiner]
US 20020133679A1 · Choi et al. · 2002 [cited by applicant]
US 20040080979A1 · Park · 2004 [cited by applicant]
US 20140198569A1 · Kim et al. · 2014 [cited by applicant]
US 20160148693A1 · Lee · 2016 [cited by applicant]
US 20170277629A1 · Li · 2017 [cited by applicant]
US 20200183615A1 · Liikanen · 2020 [cited by applicant]
US 20210055990A1 · Iwasaki et al. · 2021 [cited by applicant]
US 20230282289A1 · Sanuki et al. · 2023 [cited by applicant]
US 20240020020A1 · Kadasani et al. · 2024 [cited by applicant]
CN 117420949A · 2024 [cited by applicant]
K. Shi, M.-Z. Xu and C.-H. Tan, “The degradation of reading performance in SONOS Flash Memory with small threshold voltage window,” 2007 International Workshop on Electron Devices and Semiconductor Technology (EDST), Be… [cited by examiner]
N. A. Othman, N. M. Karim, M. Sufyan and N. Soin, “Impact of processing parameters on low-voltage power MOSFET threshold voltage considering defect generation,” RSM 2013 IEEE Regional Symposium on Micro and Nanoelectron… [cited by examiner]
Akturk, I, et al., “Decoupled Control and Data Processing for Approximate Near-Threshold Voltage Computing”, in IEEE Micro, vol. 35, No. 4, (Jul.-Aug. 2015), 70-78. [cited by applicant]
Cai, Yu, et al., “Threshold Voltage Distribution in MLC NAND Flash Memory:Characterization, Analysis, and Modeling”, 1DSSC, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA E… [cited by applicant]
Gebregiorgis, A, et al., “Reliability analysis and mitigation of near threshold caches”, International Mixed Signals Testing Workshop (IMSTW), Thessaloniki, Greece, (2017), 1-6. [cited by applicant]
Jiang, C, et al., “Near-threshold SRAM design with dynamic write-assist circuitry”, International Conference on Computer, Information and Telecommunication Systems (CITS), Kunming, China, (2016), 1-5. [cited by applicant]
Wang, Wei, et al., “Understanding the impact of threshold voltage on MLC flash memory performance and reliability”, In Proceedings of the 28th ACM international conference on Supercomputing (ICS '14). Association for Co… [cited by applicant]