Stacked dies for machine learning accelerator
A device is disclosed. The device includes a machine learning die including a memory and one or more machine learning accelerators; and a processing core die stacked with the machine learning die, the processing core die being configured to execute shader programs for controlling operations on the machine learning die, wherein the memory is configurable as either or both of a cache and a directly accessible memory.
1 . A device, comprising:
a machine learning die including a memory and one or more machine learning accelerators; and
a processing core die stacked with the machine learning die, the processing core die being configured to execute shader programs for controlling operations on the machine learning die,
wherein each machine learning accelerator is coupled to a local memory portion, to each other machine learning accelerator via a memory interconnect, and to the processing core die via an inter-die interconnect,
wherein the memory is configurable as including both a cache and a directly accessible memory,
wherein the memory includes a portion configured to switch between being used as a cache and being used as a directly accessible memory, wherein the switching comprises altering how much of the memory is used as the cache based on a specified amount; and
wherein the cache is configured to perform caching operations for the processing core die and the directly accessible memory is configured to perform memory operations for the machine learning die.
2 . The device of claim 1 , wherein the machine learning accelerators are configured to perform matrix multiplication using data in the memory.
3 . The device of claim 1 , wherein the machine learning die and the processing core die are coupled via one or more inter-die interconnects.
4 . The device of claim 1 , wherein the processor core die is configured to modify a portion of the memory from being used for the one or more machine learning accelerators to being used as a cache for the processor core die.
5 . The device of claim 1 , wherein the processor core die is configured to modify a portion of the memory from being used as a cache for the APD core die to being used for the one or more machine learning accelerators.
6 . The device of claim 1 , wherein the processor core die is configured to execute shader instructions for storing data into the memory.
7 . The device of claim 1 , wherein the machine learning die further includes one or more controllers that control operations of the memory and the machine learning accelerators.
8 . The device of claim 7 , wherein the machine learning die further includes memory interconnects that couple the one or more controllers together.
9 . The device of claim 8 , wherein the memory interconnects are configured to provide data from one portion of the memory to a controller local to a different portion of the memory.
10 . A method, comprising:
executing a shader program on an accelerated processing device (“APD”) core die;
in accordance with instructions of the shader program, directing a set of machine learning (“ML”) arithmetic logic units (“ALUs”) of an ML accelerator die to perform a set of machine learning tasks, via one or more inter-die interconnects, wherein the ML accelerator die includes a memory, wherein the ML accelerator die is stacked with the APD core die, wherein the ML accelerator die includes one or more machine learning accelerators, and wherein each machine learning accelerator is coupled to a local memory portion, to each other machine learning accelerator via a memory interconnect, and to the APD core die via an inter-die interconnect,;
performing the set of machine learning tasks with ML ALUs; and
configuring the memory as both a cache and a directly accessible memory, wherein the cache is configured to perform caching operations for the APD core die and the directly accessible memory is configured to perform memory operations for the machine learning die, wherein the memory includes a portion configured to switch between being used as a cache and being used as a directly accessible memory, wherein the switching comprises altering how much of the memory is used as the cache based on a specified amount.
11 . The method of claim 10 , wherein the machine learning accelerators are configured to perform matrix multiplication using data in the memory.
12 . The method of claim 10 , wherein the machine learning die and the APD core die are coupled via one or more inter-die interconnects.
13 . The method of claim 10 , wherein the APD core die is configured to modify a portion of the memory from being used for the one or more machine learning accelerators to being used as a cache for the APD core die.
14 . The method of claim 10 , wherein the APD core die is configured to modify a portion of the memory from being used as a cache for the APD core die to being used for the one or more machine learning accelerators.
15 . The method of claim 10 , wherein the APD core die is configured to execute shader instructions for storing data into the memory.
16 . The method of claim 10 , wherein the machine learning die further includes one or more controllers that control operations of the memory and the machine learning accelerators.
17 . The method of claim 16 , wherein the machine learning die further includes memory interconnects that couple the one or more controllers together.
18 . The method of claim 17 , wherein the memory interconnects are configured to provide data from one portion of the memory to a controller local to a different portion of the memory.
19 . A device, comprising:
a processor; and
an accelerated processing device (“APD”) including:
a machine learning die including a memory and one or more machine learning accelerators; and
a processing core die stacked with the machine learning die, the processing core die being configured to execute shader programs for controlling operations on the machine learning die, one or more of the shader programs being specified by the processor,
wherein each machine learning accelerator is coupled to a local memory portion, to each other machine learning accelerator via a memory interconnect, and to the processing core die via an inter-die interconnect,
wherein the memory is configurable as including both a cache and a directly accessible memory,
wherein the memory includes a portion configured to switch between being used as a cache and being used as a directly accessible memory, wherein the switching comprises altering how much of the memory is used as the cache based on a specified amount; and
wherein the cache is configured to perform caching operations for the processing core die and the directly accessible memory is configured to perform memory operations for the machine learning die.
20 . The device of claim 19 , wherein the machine learning accelerators are configured to perform matrix multiplication using data in the memory.