Systems and methods for low power common electrode voltage generation for displays
A system, circuit, and method for implementing a low power common electrode voltage for a display (e.g., LcoS display) having transistors with low to moderate breakdown voltages may include a first and a second low voltage amplifier, wherein the first amplifier generates a pixel voltage and the second amplifier generates a predetermined voltage. The circuit may include a common electrode circuit coupled to the first and second amplifier to generate a common electrode voltage. Particularly, the circuit may include a control circuit coupled to the common electrode circuit, wherein, during a first phase, the control circuit selectively controls the common electrode circuit to generate a low common electrode voltage based upon a negative value of the predetermined voltage. Further, during a second phase, the control circuit selectively controls the common electrode circuit to generate a high common electrode voltage based upon the sum of the predetermined voltage and the pixel voltage.
1 . A digital drive device for a display panel having a plurality of pixels, the digital drive device comprising:
a common electrode circuit coupled to a common electrode node coupled to the plurality of pixels, the common electrode circuit being configured to vary a common electrode voltage of the common electrode node to maintain a voltage balance across the display panel.
2 . The digital drive device of claim 1 , further comprising:
a bit plane memory storing bit-plane values that determine a pixel voltage to be applied to a pixel electrode of each of the plurality of pixels,
the digital drive device being configured to control the pixel voltage of each pixel to switch between a maximum pixel voltage and a minimum pixel voltage based upon a corresponding bit-plane value for each pixel.
3 . The digital drive device of claim 2 , wherein:
the common electrode circuit is configured to:
generate a predetermined voltage; and
switch the common electrode voltage between:
a first voltage that is equal to the minimum pixel voltage minus the predetermined voltage; and
a second voltage that is equal to the maximum pixel voltage plus the predetermined voltage.
4 . The digital drive device of claim 3 , wherein the common electrode circuit comprises:
a first capacitive element having a first node and a second node;
a first switch circuit configured, in response to a clock signal, to switch the first node of the first capacitive element between a node configured to receive the maximum pixel voltage and a node configured to receive the minimum pixel voltage;
a second switch circuit configured, in response to the clock signal, to switch the second node of the first capacitive element between a node configured to receive the predetermined voltage and the common electrode node;
a second capacitive element having a first node and a second node;
a third switch circuit configured, in response to the clock signal, to switch the first node of the second capacitive element between the common electrode node and a node configured to receive the minimum pixel voltage; and
a fourth switch circuit configured, in response to the clock signal, to switch the second node of the second capacitive element between a node configured to receive the predetermined voltage and a node configured to receive the minimum pixel voltage.
5 . The digital drive device of claim 4 , wherein each of the first and second capacitive elements comprises a single capacitor.
6 . The digital drive device of claim 4 , wherein:
each of the switch circuits comprises a series connected pair of complementary field effect transistors; and
each of the complementary field effect transistors including a control node configured to receive the clock signal,
an output node being formed at an interconnection of the pair of complementary field effect transistors and the output node coupled to the first or second node of the corresponding one of the first and second capacitive elements.
7 . The digital drive device of claim 3 , wherein:
the common electrode circuit comprises a voltage divider configured to generate an offset voltage; and
the common electrode circuit is configured to generate:
during a first phase, a low common voltage for the first voltage based on the offset voltage; and
during a second phase, a high common voltage for the second voltage equal to a sum of the offset voltage, the predetermined voltage, and the maximum pixel voltage.
8 . The digital drive device of claim 3 , wherein the predetermined voltage has a value of 0V to 2V.
9 . The digital drive device of claim 2 , wherein the maximum pixel voltage has a value of 1.2V to 4V, and the minimum pixel voltage has a value of 0V to −2.8V.
10 . The digital drive device of claim 1 , wherein the common electrode circuit and the display panel are formed in a same integrated circuit.
11 . A method, comprising:
controlling a common electrode circuit to vary a common electrode voltage supplied on a common electrode coupled to a plurality of pixels of a display panel to maintain a voltage balance across the display panel.
12 . The method of claim 11 , further comprising:
applying a pixel voltage to a pixel electrode of a pixel of the plurality of pixels.
13 . The method of claim 12 , wherein applying the pixel voltage to the pixel electrode comprises:
controlling the pixel voltage to switch between a maximum pixel voltage and a minimum pixel voltage based upon a bit-plane value for the pixel.
14 . The method of claim 13 , wherein controlling the common electrode circuit further comprises controlling switching of a plurality of capacitive elements to vary the common electrode voltage between:
a first voltage that is equal to the minimum pixel voltage minus a predetermined voltage; and
a second voltage that is equal to a maximum pixel voltage plus the predetermined voltage.
15 . The method of claim 14 , wherein controlling switching of the plurality of capacitive elements comprises:
during a first phase of operation:
coupling a first one of the plurality of capacitive elements between a node configured to receive the minimum pixel voltage and a node configured to receive the predetermined voltage; and
coupling a second one of the plurality of capacitive elements between the node configured to receive the minimum pixel voltage and the common electrode.
16 . The method of claim 15 , wherein controlling switching of the plurality of capacitive elements comprises:
during a second of phase of operation:
coupling the first one of the plurality of capacitive elements between a node configured to receive the maximum pixel voltage and the common electrode; and
coupling the second one of the plurality of capacitive elements between the node configured to receive the minimum pixel voltage and the node configured to receive the predetermined voltage.
17 . The method of claim 14 , wherein the predetermined voltage has a value of 0V to 2V.
18 . The method of claim 13 , wherein the maximum pixel voltage has a value of 1.2V to 4V, and the minimum pixel voltage has a value of 0V to −2.8V.
19 . A display system for displaying an image comprising:
a digital drive device configured to:
apply a pixel voltage to a pixel electrode of a pixel of a plurality of pixels of a display panel; and
vary a common electrode voltage supplied on a common electrode coupled to the plurality of pixels to maintain a voltage balance across the display panel.
20 . The display system of claim 19 , further comprising:
the display panel, comprising a liquid crystal on silicon (LCOS) display panel.