Memory device and operation method with optimized read level
A memory device includes memory cells coupled to a same word line and bit lines, respectively, and a peripheral circuit coupled to the memory cells through the word and bit lines. Each memory cell is in one state. The peripheral circuit is configured to determine a first number of a first set of the memory cells and a second number of a second set of the memory cells in parallel. Threshold voltages of the first set of the memory cells are between a first voltage and a second voltage larger than the first voltage. Threshold voltages of the second set of the memory cells are between the second voltage and a third voltage larger than the second voltage. The peripheral circuit is also configured to determine a first read level corresponding to a first state based on the first number and the second number.
1 . A memory device, comprising:
memory cells coupled to a same word line and bit lines, respectively, wherein each of the memory cells is in one of states; and
a peripheral circuit coupled to the memory cells through the word line and the bit lines, and configured to:
determine a first number of a first set of the memory cells and a second number of a second set of the memory cells in parallel, threshold voltages of the first set of the memory cells being between a first voltage and a second voltage larger than the first voltage, threshold voltages of the second set of the memory cells being between the second voltage and a third voltage larger than the second voltage;
apply a reference voltage to the same word line to determine a first read level corresponding to a first state of the states based on the first number of the first set of the memory cells and the second number of the second set of the memory cells; and
send information associated with the first read level to a memory controller,
wherein to determine the first number of the first set of memory cells and the second number of the second set of memory cells, the peripheral circuit is configured to:
determine the first number of the first set of memory cells as a first difference between a third number of memory cells in a first reference threshold interval corresponding to the reference voltage and the first voltage and a fourth number of memory cells in a second reference threshold interval corresponding to the reference voltage and the second voltage; and
determine the second number of the second set of memory cells as a second difference between the fourth number of memory cells in the second reference threshold interval and a fifth number of memory cells in a third reference threshold interval corresponding to the reference threshold and the third voltage.
2 . The memory device of claim 1 , wherein the peripheral circuit is further configured to:
determine the first read level corresponding to the first state based on a comparison between the first number of the first set of the memory cells and the second number of the second set of the memory cells.
3 . The memory device of claim 1 , wherein:
a voltage of the first read level corresponding to the first state is equal to or larger than the third voltage when the first number is larger than the second number;
the voltage of the first read level corresponding to the first state is equal to or smaller than the first voltage when the first number is smaller than the second number; and
the voltage of the first read level corresponding to the first state is equal to the second voltage when the first number is the same as the second number.
4 . The memory device of claim 1 , wherein a difference between the second voltage and the first voltage is the same as a difference between the third voltage and the second voltage.
5 . The memory device of claim 1 , wherein:
threshold voltages of the memory cells have distributions corresponding to the states, respectively;
the first, second, and third voltages are between centers of two adjacent distributions of the distributions; and
a voltage of the first read level is at a valley between the two adjacent distributions.
6 . The memory device of claim 5 , wherein to determine the first and second numbers, the peripheral circuit comprises:
page buffers coupled to the memory cells through the bit lines, respectively, and configured to:
count a first number of times that a threshold voltage of a memory cell of the memory cells is in the first reference threshold interval corresponding to the reference voltage and the first voltage, the first number of times corresponding to the third number of memory cells;
count a second number of times that a threshold voltage of a memory cell of the memory cells is in the second reference threshold interval corresponding to the reference voltage and the second voltage, the second number of time corresponding to the fourth number of memory cells; and
count a third number of times that a threshold voltage of a memory cell of the memory cells is in the third reference threshold voltage interval corresponding to the reference voltage and the third voltage, the third number of times corresponding to the fifth number of memory cells; and
control logic coupled to the page buffers and configured to:
calculate the first difference as a difference between the second number of times and the first number of times to determine the first number of the first set of the memory cells; and
calculate the second difference as a difference between the third number of times and the second number of times to determine the second number of the second set of the memory cells.
7 . The memory device of claim 6 , wherein the reference voltage is within one of the two adjacent distributions and is smaller than the first voltage.
8 . The memory device of claim 7 , wherein to determine the first and second numbers, the page buffers are further configured to:
identify each of the memory cells that has a threshold voltage smaller than the reference voltage; and
inhibit the memory cells identified that have a threshold voltage smaller than the reference voltage when determining the first number of times, the second number of times, and the third number of times.
9 . The memory device of claim 1 , wherein to determine the first and second numbers, the peripheral circuit further configured to:
pre-charge a first group of the bit lines, a second group of the bit lines, and a third group of the bit lines in parallel by applying a same reference voltage to the word line.
10 . The memory device of claim 9 , wherein the peripheral circuit is further configured to:
pre-charge the first group of the bit lines for a first sense develop time, the second group of the bit lines for a second sense develop time, and the third group of the bit lines for a third sense develop time, the third sense develop time being longer than the second sense develop time, and the second sense develop time being longer than the first sense develop time.
11 . The memory device of claim 1 , wherein the peripheral circuit is further configured to:
determine a first offset associated with the first read level corresponding to the first state.
12 . The memory device of claim 11 , wherein the peripheral circuit is further configured to:
determine the first offset corresponding to the first state between a voltage of the first read level and a first default read voltage corresponding to the first state; and
determine a second offset corresponding to a second state of the states based, at least in part, on the first offset.
13 . The memory device of claim 12 , wherein the peripheral circuit is further configured to:
determine a second read level corresponding to the second state based, at least in part, on the second offset and a second default read voltage corresponding to the second state.
14 . The memory device of claim 1 , wherein the peripheral circuit is further configured to:
determine a second read level corresponding to a second state based, at least in part, on the first read level.
15 . A memory system, comprising:
a memory device configured to store data and comprising:
memory cells coupled to a same word line and bit lines, respectively, wherein each of the memory cells is in one of states; and
a peripheral circuit coupled to the memory cells through the word line and the bit lines, and configured to:
determine a first number of a first set of the memory cells and a second number of a second set of the memory cells in parallel, threshold voltages of the first set of the memory cells being between a first voltage and a second voltage larger than the first voltage, threshold voltages of the second set of the memory cells being between the second voltage and a third voltage larger than the second voltage;
apply a reference voltage to the same word line to determine a read level corresponding to a first state of the states based on the first number of the first set of the memory cells and the second number of the second set of the memory cells; and
send information associated with the read level to a memory controller,
wherein the memory controller is coupled to the memory device and configured to send a command to the peripheral circuit to cause the peripheral circuit to apply the reference voltage to the same word line to determine the read level, and
wherein to determine the first number of the first set of memory cells and the second number of the second set of memory cells, the peripheral circuit is configured to:
determine the first number of the first set of memory cells as a first difference between a third number of memory cells in a first reference threshold interval corresponding to the reference voltage and the first voltage and a fourth number of memory cells in a second reference threshold interval corresponding to the reference voltage and the second voltage; and
determine the second number of the second set of memory cells as a second difference between the fourth number of memory cells in the second reference threshold interval and a fifth number of memory cells in a third reference threshold interval corresponding to the reference threshold and the third voltage.
16 . The memory system of claim 15 , wherein the memory controller is further configured to:
determine an offset corresponding to a second state of the states based, at least in part, on the information associated with the read level.
17 . A method for operating a memory device, comprising:
determining a first number of a first set of memory cells and a second number of a second set of the memory cells in parallel, the memory cells being coupled to a same word line and bit lines, respectively, each of the memory cells being in one of states, threshold voltages of the first set of the memory cells being between a first voltage and a second voltage larger than the first voltage, threshold voltages of the second set of the memory cells being between the second voltage and a third voltage larger than the second voltage;
determining a read level corresponding to a first state of the states based on the first number of the first set of the memory cells and the second number of the second set of the memory cells by applying a reference voltage to the same word line; and
sending information associated with the read level to a memory controller,
wherein determining the first number of the first set of memory cells and the second number of the second set of memory cells comprises:
determining the first number of the first set of memory cells as a first difference between a third number of memory cells in a first reference threshold interval corresponding to the reference voltage and the first voltage and a fourth number of memory cells in a second reference threshold interval corresponding to the reference voltage and the second voltage; and
determining the second number of the second set of memory cells as a second difference between the fourth number of memory cells in the second reference threshold interval and a fifth number of memory cells in a third reference threshold interval corresponding to the reference threshold and the third voltage.
18 . The method of claim 17 , by applying a same reference voltage to the word line, further comprising:
pre-charging a first group of the bit lines for a first sense develop time;
pre-charging a second group of the bit lines for a second sense develop time; and
pre-charging a third group of the bit lines for a third sense develop time, wherein the third sense develop time being longer than the second sense develop time, and the second sense develop time being longer than the first sense develop time.
19 . The method of claim 17 , further comprising:
determining a first offset corresponding to the first state between a voltage of the read level and a first default read voltage corresponding to the first state; and
determining a second offset corresponding to a second state of the states based, at least in part, on the first offset.
20 . The memory device of claim 1 , wherein:
the first number of the first set of memory cells is associated with a first unit threshold voltage interval corresponding to the first voltage and the second voltage, and
the second number of the second set of memory cells is associated with a second unit threshold voltage interval corresponding to the second voltage and the third voltage.