Memory device and operating method of the memory device
There are provided a memory device and an operating method of the memory device. The memory device includes: a memory block including a plurality of sub-blocks; a peripheral circuit for performing first program and erase operations in a first manner in a first sub-block, among the plurality of sub-blocks, and performing second program and erase operations in a second manner in a second sub-block, among the plurality of sub-blocks; and a control circuit configured to, when a cycling number of the second program and erase operations that are performed in the second sub-block is equal to or greater than a reference number, control the peripheral circuit to perform a compensation operation that compensates for a threshold voltage of memory cells included in the first sub-block.
1 . A memory device comprising:
a memory block including a plurality of sub-blocks;
a peripheral circuit configured to perform a first program operation in a first manner in a first sub-block, among the plurality of sub-blocks, and configured to perform a second program operation in a second manner in a second sub-block, among the plurality of sub-blocks; and
a control circuit configured to, when a program number of the second program operation that is performed in the second sub-block is equal to or greater than a reference number, control the peripheral circuit to perform a compensation operation that compensates for threshold voltages of memory cells included in the first sub-block.
2 . The memory device of claim 1 , wherein the peripheral circuit performs the first program operation in the first manner in the first sub-block and then performs the second program operation in the second manner in the second sub-block.
3 . The memory device of claim 1 , wherein, when the program number is equal to or greater than the reference number, the control circuit sets an offset in each of a re-erase operation and a re-program operation, which are to be performed in the compensation operation.
4 . The memory device of claim 3 , wherein the control circuit controls the peripheral circuit to increase an erase voltage to be used for the re-erase operation by setting the offset in the erase voltage.
5 . The memory device of claim 3 , wherein the control circuit controls the peripheral circuit to increase a start program voltage to be used for the re-program operation by setting the offset in the start program voltage.
6 . The memory device of claim 3 , wherein the control circuit controls the peripheral circuit to increase a step voltage corresponding to a voltage difference between program voltages that are used for the re-program operation by setting the offset in the step voltage.
7 . The memory device of claim 3 , wherein the control circuit controls the peripheral circuit to continuously perform the re-program operation after the re-erase operation is performed.
8 . The memory device of claim 1 , wherein, when the program number is less than the reference number, the control circuit controls the peripheral circuit to perform the second program operation and a second erase operation in the second sub-block until the program number becomes equal to or greater than the reference number.
9 . The memory device of claim 1 , wherein the first and second manners are different program manners.
10 . The memory device of claim 1 , wherein the control circuit controls the peripheral circuit to perform a third program operation in a third manner in a third sub-block, among the plurality of sub-blocks, when the compensation operation of the first sub-block is completed.
11 . The memory device of claim 10 , wherein the third manner is a program manner different from the first and second manners.
12 . The memory device of claim 11 , wherein the first to third manners are selected from a single level cell (SLC) manner, a multi-level cell (MLC) manner, a triple level cell (TLC) manner, and a quad level cell (QLC) manner.
13 . A method of operating a memory device, the method comprising:
performing a first program operation in a first manner in a first sub-block included in a memory block;
performing a second program operation in a second manner in a second sub-block included in the memory block;
comparing a program number of the second program operation that is performed in the second sub-block with a reference number; and
performing a compensation operation that compensates for a threshold voltage of memory cells included in the first sub-block when the program number is equal to or greater than the reference number.
14 . The method of claim 13 , wherein the first and second manners are different program manners.
15 . The method of claim 13 , wherein the first and second manners are selected from a single level cell (SLC) manner, a multi-level cell (MLC) manner, a triple level cell (TLC) manner, and a quad level cell (QLC) manner.
16 . The method of claim 13 , wherein the performing of the compensation operation includes:
setting an offset;
performing a re-erase operation in which the offset is set in the first sub-block; and
performing a re-program operation in which the offset is set in the first sub-block.
17 . The method of claim 16 , wherein, in the setting of the offset, an erase voltage to be used for the re-erase operation is set higher than a default level.
18 . The method of claim 16 , wherein, in the setting of the offset, a step voltage corresponding to a voltage difference between program voltages to be used in the program operation is set higher than a default level.
19 . The method of claim 16 , wherein, in the setting of the offset, a start program voltage to be used for the program operation is set higher than a default level.
20 . The method of claim 13 , wherein, when the program number is less than the reference number, the second program operation and a second erase operation are performed in the second sub-block until the program number becomes equal to or greater than the reference number.
21 . The method of claim 13 , wherein, which the compensation operation of the first sub-block is completed, a program operation is performed in a third manner in a third sub-block included in the memory block.
22 . The method of claim 21 , wherein the third manner is a program manner different from the first and second manners.