Methods for forming stacked layers and devices formed thereof
A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.
1 . A method comprising:
forming a first semiconductor layer;
forming a passivation layer over the first semiconductor layer;
forming a second semiconductor layer over the passivation layer;
removing the first semiconductor layer and the passivation layer to leave a space under the second semiconductor layer; and
forming a gate stack, with a portion of the gate stack being in the space.
2 . The method of claim 1 , wherein the first semiconductor layer and the second semiconductor layer are formed of different semiconductor materials.
3 . The method of claim 1 , wherein the gate stack comprises a first portion overlapping, and a second portion overlapped by, the second semiconductor layer.
4 . The method of claim 1 , wherein the forming the first semiconductor layer and the forming the passivation layer comprise:
depositing the first semiconductor layer through a conformal process, wherein the first semiconductor layer comprises a bottom portion at a bottom of a trench in a semiconductor substrate, and a sidewall portion on a sidewall of the semiconductor substrate;
passivating a surface portion of the first semiconductor layer to form the passivation layer; and
removing the sidewall portion of the passivation layer, with the bottom portion left.
5 . The method of claim 4 , wherein the passivating is anisotropic, and the removing the sidewall portion of the passivation layer comprises an isotropic etching process.
6 . The method of claim 4 , wherein the passivating the first semiconductor layer results in both of a horizontal portion and a vertical portion of the first semiconductor layer to be partially converted into the passivation layer.
7 . The method of claim 4 , wherein the passivating comprising oxidizing.
8 . The method of claim 1 , wherein the forming the first semiconductor layer comprises depositing a silicon germanium layer or a carbon-doped silicon layer, and the forming the second semiconductor layer comprises depositing a silicon layer.
9 . The method of claim 1 further comprising patterning the first semiconductor layer, the passivation layer, and the second semiconductor layer to form a multi-layer stack.
10 . The method of claim 1 further comprising etching a semiconductor substrate to form a trench, wherein the first semiconductor layer, the passivation layer, and the second semiconductor layer comprise lower portions in the trench.
11 . The method of claim 10 further comprising:
patterning the lower portions to form a narrowed multi-layer stack; and
forming shallow trench isolations on opposite sides of the narrowed multi-layer stack.
12 . The method of claim 11 , wherein the removing the first semiconductor layer and the passivation layer are performed after the shallow trench isolations are formed.
13 . A method comprising:
forming a trench in a substrate;
depositing a first semiconductor layer comprising a portion in the trench;
forming a first passivation layer on the first semiconductor layer, wherein the first passivation layer is formed by adding first elements into a surface layer of the first semiconductor layer;
depositing a second semiconductor layer on the first passivation layer, wherein the first semiconductor layer and the second semiconductor layer comprise different semiconductor materials;
forming a second passivation layer on the second semiconductor layer, wherein the second passivation layer is formed by adding second elements into a second surface layer of the second semiconductor layer; and
forming a gate-all-around (GAA) transistor based on the first semiconductor layer, the first passivation layer, the second semiconductor layer, and the second passivation layer, wherein the second semiconductor layer acts as a channel of the GAA transistor.
14 . The method of claim 13 , wherein the forming the GAA transistor further comprises:
patterning the first semiconductor layer, the first passivation layer, the second semiconductor layer, and the second passivation layer to form a multi-layer stack;
removing the first semiconductor layer, the first passivation layer, and the second passivation layer from the multi-layer stack; and
forming a gate stack encircling the second semiconductor layer.
15 . The method of claim 14 , wherein in the patterning, a portion of the substrate underlying the substrate is etched to form a semiconductor strip, and wherein the multi-layer stack overlaps the semiconductor strip.
16 . The method of claim 13 , wherein a first top surface of the second passivation layer is lower than a second top surface of the substrate.
17 . A method comprising:
repeating a plurality of cycles to form a multi-layer stack in a trench in a substrate, wherein a cycle in the plurality of cycles comprises:
growing a first semiconductor layer in the trench;
forming a first passivation layer overlapping the first semiconductor layer; and
forming a second semiconductor layer over the first passivation layer;
patterning the multi-layer stack;
generating a space overlapping the first semiconductor layer, wherein the generating the space comprises removing the first passivation layer and the second semiconductor layer; and
forming a gate stack, with a portion of the gate stack in the space.
18 . The method of claim 17 , wherein the cycle further comprises:
forming a second passivation layer over the second semiconductor layer, wherein the generating the space further comprises removing the second passivation layer.
19 . The method of claim 18 , wherein the gate stack encircles the first semiconductor layer.
20 . The method of claim 18 , wherein the trench has a top width and a bottom width greater than the top width.