Semiconductor memory device
A semiconductor memory device includes first and second memory cell arrays. The first array includes a first semiconductor portion, extending in a first direction, on which a first memory cell and a first select transistor are formed, a first word line connected to the first cell, a first select gate line connected to the first transistor, and a first bit line connected to the first semiconductor portion. The second array includes a second semiconductor portion, extending along the first direction, on which a second memory cell and a second select transistor are formed, a second word line connected to the second cell, a second select gate line connected to the second transistor, and a second bit line connected to the second semiconductor portion. The first and second word lines are electrically connected, but the first and second select gate lines are not electrically connected.
1 . A semiconductor memory device, comprising:
a first memory cell array;
a second memory cell array above the first memory cell array in a first direction; and
a first driver transistor below the first memory cell array in the first direction, wherein
the first memory cell array includes:
a first semiconductor portion that extends along the first direction, a first memory cell and a first select transistor being formed on the first semiconductor portion,
a first word line connected to a gate of the first memory cell,
a first select gate line connected to a gate of the first select transistor,
a first bit line electrically connected to the first semiconductor portion,
a first contact connected to the first word line and extending along the first direction,
a first wiring connected to the first contact and extending along a second direction crossing the first direction,
a second contact connected to the first wiring and extending along the first direction, and
a first pad above the second contact and electrically connected to the first and second contacts,
the first bit line being located between the first driver transistor and the first select gate line in the first direction,
the second memory cell array includes:
a second semiconductor portion that extends along the first direction, a second memory cell and a second select transistor being formed on the second semiconductor portion,
a second word line connected to a gate of the second memory cell,
a second select gate line connected to a gate of the second select transistor,
a second bit line electrically connected to the second semiconductor portion,
a third contact connected to the second word line and extending along the first direction,
a second wiring connected to the third contact and extending along the second direction, and
a second pad connected to the second wiring and in direct contact with the first pad, the second pad being electrically connected to the third contact,
the first and second word lines are electrically connected to each other,
the first driver transistor is electrically connected to the first and second word lines,
the first and second select gate lines are not electrically connected to each other, and
the second memory cell array includes no contacts that extend along the first direction and are located so as to overlap the second pad when viewed along the first direction.
2 . The semiconductor memory device according to claim 1 , wherein the first and second bit lines are electrically connected to each other.
3 . The semiconductor memory device according to claim 2 , further comprising:
a sense amplifier;
a third wiring extending along the first direction and connected to the first and second bit lines; and
a fourth wiring extending along the first direction and connected to the third wiring and the sense amplifier.
4 . The semiconductor memory device according to claim 1 , further comprising:
a sense amplifier; and
a selection circuit connected to the sense amplifier and configured to select one of the first and second bit lines to be connected to the sense amplifier.
5 . The semiconductor memory device according to claim 4 , wherein
the selection circuit includes a select transistor selectively connectable to one of the first and second bit lines via a wiring that extends from the select transistor along the first direction.
6 . The semiconductor memory device according to claim 1 , wherein
the first memory cell array further includes a third bit line that aligns with the first bit line along the second direction and is not electrically connected to the first bit line,
the second memory cell array further includes a fourth bit line that aligns with the second bit line along the second direction and is not electrically connected to the second bit line,
the first and second bit lines are connected to each other via a wiring extending along the first direction, and
the third and fourth bit lines are connected to each other via a wiring extending along the first direction.
7 . The semiconductor memory device according to claim 6 , wherein a sum of lengths of the first and second bit lines is equal to a sum of lengths of the third and fourth bit lines.
8 . The semiconductor memory device according to claim 7 , wherein the first bit line is shorter than the second and third bit lines.
9 . The semiconductor memory device according to claim 6 , further comprising:
a sense amplifier; and
a selection circuit connected to the sense amplifier and configured to select one of the first and third bit lines to be connected to the sense amplifier.
10 . The semiconductor memory device according to claim 1 , wherein the second semiconductor portion is above the first semiconductor portion in the first direction.
11 . The semiconductor memory device according to claim 1 , wherein the second bit line is above the first bit line in the first direction.
12 . The semiconductor memory device according to claim 1 , wherein the second contact penetrates the first word line.
13 . The semiconductor memory device according to claim 1 , further comprising:
a sense amplifier provided below the first memory cell array and electrically connected to the first and second bit lines;
a fourth contact extending along the first direction in the first memory cell array and electrically connected to the first bit line;
a third pad on the fourth contact; and
a fourth pad electrically connected to the second bit line and in direct contact with the third pad, wherein
the second memory cell array includes no contacts that extend along the first direction and are located so as to overlap the fourth pad when viewed along the first direction.