Granted Patent B2

US 12,464,761 · App. 18/072,201 · Granted Nov 4, 2025

Inventors: Martin B. Mollat (Gainesville, TX); Henry L. Edwards (Garland, TX); Alexei Sadovnikov (Sunnyvale, CA)

Assignee: Texas Instruments Incorporated

H10D30/603H01L21/76202H10D30/0221H10D30/65H10D64/111H10D64/112H10D84/017H10D84/038H10D30/601

Abstract

Claims (33)

1 . An integrated circuit, comprising:

a source region and a drain region spaced apart and extending into a semiconductor layer having a first conductivity type, the source region and the drain region having an opposite second conductivity type;

a gate electrode extending between the source and the drain regions; and

a dielectric layer between the gate electrode and the semiconductor layer, the dielectric layer including a first portion having a first thickness in contact with the semiconductor layer, and a second portion with a greater second thickness over the semiconductor layer, a lateral perimeter of the second portion surrounding the source region and including:

a first edge having a first linear segment extending over the semiconductor layer and between the source region and the drain region along a first direction; and

a second edge having a second linear segment extending over the semiconductor layer along a different second direction; and

a fillet of the second portion connecting the first linear segment and the second linear segment of the lateral perimeter.

2 . The integrated circuit of claim 1 , wherein the second portion of the dielectric layer touches a well region having the second conductivity type.

3 . The integrated circuit of claim 1 , wherein the fillet has a constant lateral radius of curvature and begins at a point on the first edge corresponding to a maximum extent of the drain region parallel to the first edge.

4 . The integrated circuit of claim 1 , wherein an edge of the fillet includes a circular arc having a radius of curvature of at least 0.25 μm.

5 . The integrated circuit of claim 1 , wherein an edge of the fillet includes a circular arc having a radius of curvature of about 1 μm.

6 . The integrated circuit of claim 1 , wherein the fillet has a fill ratio of at least 5%.

7 . The integrated circuit of claim 1 , wherein the fillet has a fill ratio of at least about 20%.

8 . An integrated circuit, comprising:

a source region between first and second drain regions, the source region and the drain regions extending into a semiconductor layer and having a first conductivity type, the semiconductor layer having an opposite second conductivity type;

a gate electrode extending between the source and the drain regions;

a dielectric layer between the gate electrode and the semiconductor layer, the dielectric layer including a first portion having a first thickness in contact with the semiconductor layer, and a second portion with a greater second thickness over the semiconductor layer, the second portion having a lateral perimeter that includes a first linear section extending on a top surface of the semiconductor layer along a first direction and a second linear section extending on the top surface of the semiconductor layer along a different second direction, and a third section joining the first and second linear sections, the third section having a lateral radius of curvature of at least 0.25 μm.

9 . The integrated circuit of claim 8 , wherein the first conductivity type is n-type and the second conductivity type is n-type.

10 . The integrated circuit of claim 8 , wherein the second portion of the dielectric layer includes a local oxidation of silicon (LOCOS) structure.

11 . The integrated circuit of claim 8 , wherein the second portion of the dielectric layer has a thickness in a range from about 20 nm to about 40 nm.

12 . The integrated circuit of claim 8 , wherein the lateral radius of curvature is at least 0.50 μm.

13 . The integrated circuit of claim 8 , wherein the lateral radius of curvature is about 1 μm.

14 . The integrated circuit of claim 8 , wherein the source region, the drain region and the gate electrode are components of a metal-oxide-semiconductor (MOS) transistor having a voltage capacity of at least 40 V between the source region and the drain region.

15 . The integrated circuit of claim 8 , further comprising a drift region having the first conductivity type extending from the drain region toward the source region, the second portion in contact with the drift region.

16 . The integrated circuit of claim 8 , wherein the third section has an edge with a piecewise-linear profile.

17 . The integrated circuit of claim 8 , wherein the second portion surrounds the source region and includes four corners having the lateral radius of curvature.

18 . A method of forming an integrated circuit, comprising:

forming a source region and a drain region spaced apart and extending into a semiconductor layer having a first conductivity type, the source region and the drain region having an opposite second conductivity type;

forming a gate electrode extending between the source and the drain regions; and

forming a dielectric layer between the gate electrode and the semiconductor layer, the dielectric layer including a first portion having a first thickness in contact with the semiconductor layer, and a second portion with a greater second thickness over the semiconductor layer, the second portion including:

a lateral perimeter that surrounds the source region and includes a first linear section extending over the semiconductor layer and between the source region and the drain region along a first direction;

a second linear section extending over the semiconductor layer along a different second direction; and

a fillet at an intersection of the first and second linear sections.

Assignments (1)

Continuity (1)

References Cited (81)