IP Library › Granted Patent US 11,362,208
Granted Patent B2
US 11,362,208 · App. 16/551,493 · Granted Jun 14, 2022

Semiconductor device having an insulator between source and drain regions and a gate electrode having a portion that covers the insulator and a portion that does not cover the insulator

Inventor: Hirofumi Kawai (Yokohama Kanagawa, JP)
Assignees: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
H01L29/7816H01L29/0626H01L29/1045
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Quick Facts
Patent No.
US 11,362,208
App. No.
16/551,493
Granted
Jun 14, 2022
Kind
B2
Abstract

A semiconductor device includes a semiconductor substrate having a source region and a drain region, a first insulator between the source region and the drain region, a gate electrode having a first end on a side thereof closer to the source region than the drain region on a portion of the semiconductor substrate that is not covered with the first insulator, and having a second end on the first insulator closer to the drain region than the source region, and a second insulator that is continuous with the second end of the gate electrode and having a portion which is on the first insulator where the first insulator is not covered with the gate electrode, is on an end of the drain region, and is in contact with the gate electrode, the first insulator, and the drain region.

Claims (21)

1. A semiconductor device comprising:

a semiconductor substrate having a source region and a drain region;

a first insulator between the source region and the drain region;

a gate electrode having a first end on a side thereof closer to the source region than the drain region on a portion of the semiconductor substrate that is not covered with the first insulator, and having a second end on the first insulator closer to the drain region than the source region;

a second insulator that is continuous with the second end of the gate electrode and having a portion which is on the first insulator where the first insulator is not covered with the gate electrode, is on an end of the drain region, and is in contact with the gate electrode, the first insulator, and the drain region;

a third insulator on an end face of the first end of the gate electrode and on an end of the source region, wherein the third insulator includes a first layer made of silicon oxide, that contacts the gate electrode and the source region, a second layer made of silicon nitride, that contacts the first layer, and a third layer made of silicon oxide, that contacts the second layer; and

an interlayer insulating film on the semiconductor substrate, the first insulator, the gate electrode, and the second insulator, wherein the interlayer insulating film does not contact the first insulator.

2. The semiconductor device according to claim 1 , wherein

the first insulator has a first end closer to the source region than the drain region, a second end closer to the drain region than the source region and a central part between the first and second ends, wherein the first and second ends are thinner than the central part.

3. The semiconductor device according to claim 2 , wherein

the first and second ends of the first insulator are progressively thinner with distance away from the central part.

4. The semiconductor device according to claim 1 , wherein

the second insulator includes

a fourth layer made of silicon oxide, that contacts the gate electrode, the first insulator, and the drain region,

a fifth layer made of silicon nitride, that is on the fourth layer, and

a sixth layer made of silicon oxide, that is on the fifth layer.

5. The semiconductor device according to claim 1 , wherein

the source region and the drain region are of a first conductivity type, and

the semiconductor substrate further includes

a first semiconductor layer of a second conductivity type that contacts the source region, and

a second semiconductor layer of the first conductivity type that contacts the drain region, the first insulator, and the first semiconductor layer.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE 1TH RECEIVING PARTY NAME AND OMISSION OF THE SECOND ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 052640 FRAME: 0753. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT . Recorded Jun 25, 2021
From: KAWAI, HIROFUMI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 056684/0085 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2020
From: KAWAI, HIROFUMI
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 052640/0753 →
Priority Claims (1)
JP JP2019-040448 · Mar 6, 2019 · national
Continuity (1)
Related Publication 20200287045A1 · Sep 10, 2020
Cited By (1)
US 12,464,761