Method for forming an interconnection structure
A method for forming an interconnection structure for a first transistor and a second transistor is provided. The first transistor includes a horizontally extending first channel portion and the second transistor includes a horizontally extending second channel portion. The channel portions are stacked above each other on a substrate. The method includes forming a conductive line extending beside and below the second channel portion, forming, on the conductive line, a first vertical interconnect structure for electrically contacting the first channel portion, and thinning the substrate from the backside to expose the conductive line from below. The method further includes forming a via hole exposing the second channel portion from below, filling the via hole with a conductive material to form a second vertical interconnect structure, and forming a conductive structure on the second vertical interconnect structure. A semiconductor device is also provided.
1 . A method for forming an interconnection structure for a first transistor and a second transistor vertically stacked on a substrate, wherein the first transistor includes a horizontally extending first channel portion and the second transistor includes a horizontally extending second channel portion, and wherein the first channel portion is arranged above the second channel portion, the method comprising:
forming, in the substrate, a conductive line extending beside and below the second channel portion;
forming, on the conductive line, a first vertical interconnect structure for electrically contacting the first channel portion;
thinning the substrate from a backside to expose the conductive line from below;
forming a via hole exposing the second channel portion from below;
filling the via hole with a conductive material to form a second vertical interconnect structure; and
forming a conductive structure on the second vertical interconnect structure.
2 . The method according to claim 1 , further comprising:
forming a bonding layer above the first vertical interconnect structure;
bonding a carrier wafer to the bonding layer; and
flipping the substrate upside down to allow processing from the backside of the substrate.
3 . The method according to claim 1 , further comprising:
depositing an insulating layer covering the conductive line and the first and second channel portions;
etching a trench in the insulating layer to expose the conductive line and the first and second channel portions;
forming spacers at sidewalls of the first and second channel portions; and
filling the trench with the conductive material forming the first vertical interconnect structure contacting the first channel portion at least partly from above.
4 . The method according to claim 3 , further comprising:
forming a bonding layer above the first vertical interconnect structure;
bonding a carrier wafer to the bonding layer; and
flipping the substrate upside down to allow processing from the backside of the substrate.
5 . The method according to claim 2 , further comprising:
forming, from the backside, a trench that is aligned with the second channel portion;
forming the via hole in a bottom of the trench; and
depositing the conductive material to fill the via hole and the trench, thereby forming the second vertical interconnect structure and the conductive structure.
6 . The method according to claim 1 , wherein an exposed portion of the conductive line and an exposed portion of the conductive structure are arranged on the same vertical level.
7 . The method according to claim 1 , further comprising:
epitaxially forming a stacked structure comprising alternating layers of a channel material and a sacrificial material;
patterning the stacked structure into a fin; and
removing the sacrificial material from at least a portion of the fin, wherein remaining portions of the channel material form the first and second channel portions.
8 . The method according to claim 7 , further comprising forming a gate structure at least partly enclosing the first and second channel portions.
9 . The method according to claim 7 , wherein the channel material is formed of Si and the sacrificial material is formed of SiGe.
10 . The method according to claim 9 , further comprising forming a gate structure at least partly enclosing the first and second channel portions.
11 . The method according to claim 1 , wherein the substrate comprises an etch stop layer, and wherein forming the conductive line comprises etching down to the etch stop layer.
12 . The method according to claim 1 , comprising forming, in the substrate, a first and a second conductive line on opposite sides of the second channel portion, wherein the first vertical interconnect structure is arranged to interconnect the second channel portion with each of the first and second conductive lines.
13 . A semiconductor device, comprising:
a first transistor and a second transistor vertically stacked on a substrate, wherein the first transistor includes a horizontally extending first channel portion and the second transistor includes a horizontally extending second channel portion, and wherein the first channel portion is arranged above the second channel portion;
a conductive line formed in the substrate and extending beside and below the second channel portion;
a first vertical interconnect structure formed on the conductive line for electrically contacting the first channel portion, wherein the substrate is configured to be thinned from a backside to expose the conductive line from below;
a via hole formed to expose the second channel portion from below;
a second vertical interconnect structure formed by filling the via hole with a conductive material; and
a conductive structure formed on the second vertical interconnect structure.
14 . The semiconductor device according to claim 13 , wherein a bottom portion of the conductive line and a bottom portion of the conductive structure are arranged at the same vertical level.