Vertical field effect transistor with minimal contact to gate erosion
A semiconductor device comprises a substrate including at least one vertical fin extending from the substrate, a bottom source/drain region beneath the at least one vertical fin, a top source/drain region disposed above the at least one vertical fin, a metal gate structure, a contact coupled to the top source/drain region and first and second contact spacers disposed on each side of the contact.
1 . A semiconductor device, comprising:
a substrate including at least one vertical fin extending from the substrate;
a bottom source/drain region beneath the at least one vertical fin;
a top source/drain region disposed above the at least one vertical fin;
a metal gate structure;
a contact coupled to the top source/drain region;
first and second contact spacers disposed on each side of the contact; and
an insulative layer disposed abutting a bottom surface of the first and second contact spacers, abutting sidewall portions of the top source/drain region and sidewall portions of the metal gate structure, and a top surface of the bottom source/drain region.
2 . The semiconductor device according to claim 1 wherein the first and second contact spacers comprise a dielectric material configured to minimize erosion between the contact and the metal gate structure.
3 . The semiconductor device according to claim 2 wherein the dielectric material of the first and second contact spacers comprise at least one of silicon nitride, silicon carbon nitride and silicon oxycarbonitride.
4 . The semiconductor device according to claim 2 further including a hard mask segment disposed adjacent a peripheral segment of at least one of the first and second contact spacers, the hard mask segment comprising a dielectric material.
5 . The semiconductor device according to claim 4 wherein the dielectric material of the hard mask segment is different from the dielectric material of the first and second contact spacers.
6 . A semiconductor device, comprising:
a substrate including first and second vertical fins extending from the substrate;
a bottom source/drain region beneath each of the first and second vertical fins;
a top source/drain region disposed above each of the first and second vertical fins;
a metal gate structure at least partially surrounding each of the first and second vertical fins;
first and second contacts respectively contact coupled to the top source/drain regions above each of the first and second vertical fins;
first and second contact spacer segments disposed on each side of the first and second contacts, the first and second contact spacer segments comprising a dielectric material; and
an insulative layer disposed abutting a bottom surface of the first and second contact spacer segments, abutting sidewall portions of the top source/drain region and sidewall portions of the metal gate structure, and a top surface of the bottom source/drain region.
7 . The semiconductor device according to claim 6 wherein adjacent contact spacer segments on adjacent sides of the first and second contacts are in contact with each other.
8 . The semiconductor device according to claim 6 wherein adjacent contact spacer segments on adjacent sides of the first and second contacts are spaced relative to each other.
9 . The semiconductor device according to claim 8 including an additional inner dielectric segment disposed between adjacent contact spacer segments on adjacent sides of the first and second contacts.
10 . The semiconductor device according to claim 9 wherein the additional inner dielectric segment comprises a dielectric material different from the dielectric material of the contact spacer segments.
11 . The semiconductor device according to claim 8 including a metallic contact segment disposed between adjacent contact spacer segments on adjacent sides of the first and second contacts.
12 . The semiconductor device according to claim 6 further including an additional peripheral dielectric segment disposed outward of an outer contact spacer segment adjacent the first contact.
13 . The semiconductor device according to claim 12 further including an additional peripheral dielectric segment disposed outward of an outer contact spacer segment adjacent the second contact.
14 . The semiconductor device according to claim 13 wherein the additional peripheral dielectric segments each comprises a dielectric material different from the dielectric material of the first and second contact spacer segments.
15 . The semiconductor device according to claim 14 wherein the additional peripheral dielectric segments comprise a dielectric material different from the dielectric material of the outer contact spacer segments.
16 . An integrated circuit comprising at least a semiconductor structure comprising:
a substrate including at least one vertical fin extending from the substrate;
a bottom source/drain region beneath the at least one vertical fin;
a top source/drain region disposed above the at least one vertical fin;
a metal gate structure;
a contact coupled to the top source/drain region; and
first and second contact spacers disposed on each side of the contact
an insulative layer disposed abutting a bottom surface of the first and second contact spacers, abutting sidewall portions of the top source/drain region and sidewall portions of the metal gate structure, and a top surface of the bottom source/drain region.
17 . The integrated circuit of claim 16 , wherein the first and second contact spacers comprise a dielectric material configured to minimize erosion between the contact and the metal gate structure.
18 . The integrated circuit of claim 17 , wherein the dielectric material of the first and second contact spacers comprise at least one of silicon nitride, silicon carbon nitride and silicon oxycarbonitride.
19 . The integrated circuit of claim 17 , the semiconductor structure further comprising a hard mask segment disposed adjacent a peripheral segment of at least one of the first and second contact spacers, the hard mask segment comprising a dielectric material.
20 . The integrated circuit of claim 19 , wherein the dielectric material of the hard mask segment is different from the dielectric material of the first and second contact spacers.