IP Library › Granted Patent US 12,464,826
Granted Patent B2
US 12,464,826 · App. 17/964,267 · Granted Nov 4, 2025

Semiconductor device

Inventor: Yasuyuki Morishita (Tokyo, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H10D89/611H10D89/10H10D89/601H10D89/921H10D89/931
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Quick Facts
Patent No.
US 12,464,826
App. No.
17/964,267
Granted
Nov 4, 2025
Kind
B2
Abstract

A semiconductor device includes an input/output cell, an IO power supply cell, a core power supply cell, and a core logic circuit arranged on a chip, and the core power supply cell includes an ESD protection circuit. The input/output cell includes a level shifter circuit and the level shifter circuit is arranged in the input/output cell. The core logic circuit is arranged outside the input/output cell. The core power supply cell is not arranged in the same row as the input/output cell, but is arranged in a third region provided between a first region in which the input/output cell and the IO power supply cell are arranged and a second region in which the core logic circuit is arranged.

Claims (8)

1 . A semiconductor device in which an input/output cell, an IO power supply cell, a core power supply cell, and a core logic circuit are arranged on a chip,

wherein the core power supply cell includes an ESD protection circuit,

wherein the input/output cell includes a level shifter circuit and the level shifter circuit is arranged in the input/output cell,

wherein the core logic circuit is arranged outside the input/output cell,

wherein the core power supply cell is not arranged in the same row as the input/output cell, but is arranged in a third region provided between a first region in which the input/output cell and the IO power supply cell are arranged and a second region in which the core logic circuit is arranged, and

wherein the core power supply cell is formed such that a long side of external dimensions thereof is shorter than a long side of an outer shape of the IO power supply cell, and a short side of external dimensions thereof is equal to or greater than a short side of the outer shape of the IO power supply cell.

2 . The semiconductor device according to claim 1 ,

wherein the core power supply cell is not arranged between the input/output cell and the core logic circuit, but is arranged in a fourth region between the IO power supply cell and the core logic circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2022
From: MORISHITA, YASUYUKI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 061448/0810 →
Priority Claims (2)
JP 2021-178382 · Oct 29, 2021 · national
JP 2022-126689 · Aug 8, 2022 · national
Continuity (1)
Related Publication 20230139094A1 · May 4, 2023
References Cited (10)
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Office Action received in Corresponding German Patent Application No. 10 2022 211 502.3, mailed Apr. 17, 2023. [cited by applicant]
Office Action dated May 7, 2025, issued in corresponding JP Application No. 2022-126689, 7 pages. [cited by applicant]