Display driving circuit, display driving method and display panel
A display driving circuit includes a first transistor, a storage subcircuit, a compensation subcircuit, a data writing subcircuit, a light-emitting control subcircuit and a reverse bias subcircuit. The storage subcircuit is connected to a control terminal of the first transistor through a first node and to the first transistor through a second node. The compensation subcircuit is connected to a first light-emitting control line, the first transistor and a power supply high-voltage terminal. The data writing subcircuit is connected to a data line, a scan line and the first node. The light-emitting control subcircuit is connected to a second light-emitting control line, a second node and an anode of the display light-emitting subcircuit, a cathode of the display light-emitting subcircuit is connected to the scan line. The reverse bias subcircuit is connected to the scan line, a third node and the power supply high-voltage terminal.
1 . A display driving circuit comprising a first transistor, the first transistor being connected to a display light-emitting subcircuit, wherein the display driving circuit further comprises:
a storage subcircuit connected to a control terminal of the first transistor through a first node and connected to a first terminal of the first transistor through a second node;
a compensation subcircuit connected to a first light-emitting control line, a second terminal of the first transistor and a power supply terminal;
a data writing subcircuit, comprising a third transistor, wherein a control terminal of the third transistor is connected to a scan line, a first terminal of the third transistor is connected to the first node, and a second terminal of the third transistor is connected to a data line, for writing a data line signal into the storage subcircuit in response to a first scan line signal, wherein a potential of the power supply terminal is less than a potential of the scan line when the scan line receives the first scan signal, and the potential of the power supply terminal is higher than the potential of the scan line when the scan line receives a second scan line signal, wherein the first scan line signal is higher than the second scan line signal in potential;
a light-emitting control subcircuit connected to a second light-emitting control line and the second node, the light-emitting control subcircuit further connected to an anode of the display light-emitting subcircuit through a third node, a cathode of the display light-emitting subcircuit being connected to the scan line, and an end of the third node is connected to the display light-emitting subcircuit, another end of the third node is connected to the light-emitting control subcircuit; and
a reverse bias subcircuit, comprising a fourth transistor, wherein a control terminal of the fourth transistor is connected to the scan line connected to the cathode of the display light-emitting subcircuit, a first terminal of the fourth transistor is connected to the third node, and a second terminal of the fourth transistor is connected to the power supply terminal, the reverse bias subcircuit being configured for being conducted to enabling a potential of anode of the display light-emitting subcircuit to be equal to the potential of the power supply terminal in response to the first scan line signal, to make a potential of the cathode of the display light-emitting subcircuit greater than the potential of anode of the display light-emitting subcircuit.
2 . The display driving circuit according to claim 1 , wherein the storage subcircuit comprises a first capacitor, the first capacitor being connected to the first node and the second node.
3 . The display driving circuit according to claim 2 , wherein the storage subcircuit further comprises a second capacitor, the second capacitor being connected to the second node and a grounding terminal.
4 . The display driving circuit according to claim 3 , wherein the compensation subcircuit comprises a second transistor, wherein a control terminal of the second transistor is connected to the first light-emitting control line, a first terminal of the second transistor is connected to the first transistor, and a second terminal of the second transistor is connected to the power supply terminal.
5 . The display driving circuit according to claim 3 , wherein the light-emitting control subcircuit comprises a fifth transistor, wherein a control terminal of the fifth transistor is connected to the second light-emitting control line, a first terminal of the fifth transistor is connected to the third node, and a second terminal of the fifth transistor is connected to the second node.
6 . The display driving circuit according to claim 3 , wherein when data voltage is written to the first node, potential of the first node changes from 0 to Vdata, potential of the second node changes from −Vth to (Cs/(Cs+Cd))*Vdata−Vth, where Cs is a capacitance of the first capacitor, and Cd is the capacitance of the second capacitor.
7 . The display driving circuit according to claim 6 , wherein when the display light-emitting subcircuit emits light, current I flowing through the display light-emitting subcircuit is:
I
=
1
/
2
*
μ
*
k
(
Cd
/
(
Cs
+
Cd
)
)
*
Vdata
)
2
where μ is a carrier mobility, k=W/L, W is a channel width of the first transistor, and L is a channel length of the first transistor.
8 . A display panel comprising:
a display driving circuit; and
a display light-emitting subcircuit connected to the display driving circuit;
wherein the display driving circuit comprises a first transistor, the first transistor being connected to the display light-emitting subcircuit, wherein the display driving circuit further comprises:
a storage subcircuit connected to a control terminal of the first transistor through a first node and connected to a first terminal of the first transistor through a second node;
a compensation subcircuit connected to a first light-emitting control line, a second terminal of the first transistor and a power supply terminal;
a data writing subcircuit, comprising a third transistor, wherein a control terminal of the third transistor is connected to a scan line, a first terminal of the third transistor is connected to the first node, and a second terminal of the third transistor is connected to a data line, for writing a data line signal into the storage subcircuit in response to a first scan line signal, wherein a potential of the power supply terminal is less than a potential of the scan line when the scan line receives the first scan signal, and the potential of the power supply terminal is higher than the potential of the scan line when the scan line receives a second scan line signal, wherein the first scan line signal is higher than the second scan line signal in potential;
a light-emitting control subcircuit connected to a second light-emitting control line and the second node, the light-emitting control subcircuit further connected to an anode of the display light-emitting subcircuit through a third node, a cathode of the display light-emitting subcircuit being connected to the scan line, and an end of the third node is connected to the display light-emitting subcircuit, another end of the third node is connected to the light-emitting control subcircuit; and
a reverse bias subcircuit, comprising a fourth transistor, wherein a control terminal of the fourth transistor is connected to the scan line connected to the cathode of the display light-emitting subcircuit, a first terminal of the fourth transistor is connected to the third node, and a second terminal of the fourth transistor is connected to the power supply terminal, the reverse bias subcircuit being configured for being conducted to enabling a potential of anode of the display light-emitting subcircuit to be equal to the potential of the power supply terminal in response to the first scan line signal, to make a potential of the cathode of the display light-emitting subcircuit greater than the potential of anode of the display light-emitting subcircuit.
9 . The display panel according to claim 8 , wherein the storage subcircuit comprises a first capacitor, the first capacitor being connected to the first node and the second node.
10 . The display panel according to claim 9 , wherein the storage subcircuit further comprises a second capacitor, the second capacitor being connected to the second node and a grounding terminal.
11 . The display panel according to claim 10 , wherein the compensation subcircuit comprises a second transistor, wherein a control terminal of the second transistor is connected to the first light-emitting control line, a first terminal of the second transistor is connected to the first transistor, and a second terminal of the second transistor is connected to the power supply terminal.
12 . The display panel according to claim 10 , wherein the light-emitting control subcircuit comprises a fifth transistor, wherein a control terminal of the fifth transistor is connected to the second light-emitting control line, a first terminal of the fifth transistor is connected to the third node, and a second terminal of the fifth transistor is connected to the second node.
13 . The display panel according to claim 10 , wherein when data voltage is written to the first node, potential of the first node changes from 0 to Vdata, potential of the second node changes from −Vth to (Cs/(Cs+Cd))*Vdata−Vth, where Cs is a capacitance of the first capacitor, and Cd is the capacitance of the second capacitor.