Nonvolatile memory device, operation method of a nonvolatile memory device, and operation method of a controller
A memory device including a first substrate, a peripheral circuit provided on the first substrate, a first metal bonding layer provided on the peripheral circuit, a second metal bonding layer directly bonded to the first metal bonding layer, a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.
1 . An operation method of a controller connected to a nonvolatile memory device, the operation method comprising:
receiving device information from the nonvolatile memory device by transmitting a first command to the nonvolatile memory device;
determining a pass/failure mode and information on a reference value based on the device information;
setting the pass/failure mode and the information on the reference value by transmitting a second command to the nonvolatile memory device; and
performing a program operation on selected memory cells of the nonvolatile memory device by transmitting a program command and data to the nonvolatile memory device,
wherein the pass/failure mode includes one of a program failure prediction mode, a program pass prediction mode, and a program pass/failure prediction mode.
2 . The method as claimed in claim 1 , wherein:
the program operation includes a plurality of program loops, and
each of the plurality of program loops includes a program step and a verification step.
3 . The method as claimed in claim 2 , wherein if the pass/failure mode is set to the program failure prediction mode, the verification step includes:
generating a first failure bit accumulated value based on first memory cells of the selected memory cells;
comparing the first failure bit accumulated value with a first failure reference value to determine a program failure;
generating a second failure bit accumulated value based on second memory cells of the selected memory cells when the first failure bit accumulated value is less than the first failure reference value; and
comparing the second failure bit accumulated value with a second failure reference value to determine a program failure, the second failure reference value being greater than the first failure reference value.
4 . The method as claimed in claim 2 , wherein if the pass/failure mode is set to the program pass prediction mode, the verification step includes:
generating a first failure bit accumulated value based on a first memory cells of the selected memory cells;
comparing the first failure bit accumulated value with a first pass reference value to determine a program pass;
generating a second failure bit accumulated value based on second memory cells of the selected memory cells when the first failure bit accumulated value is greater than the first pass reference value; and
comparing the second failure bit accumulated value with a second pass reference value to determine a program pass, the second pass reference value being greater than the first pass reference value.
5 . The method as claimed in claim 2 , wherein if the pass/failure mode is set to the program pass/failure prediction mode, the verification step includes:
generating a first failure bit accumulated value based on first memory cells of the selected memory cells;
comparing the first failure bit accumulated value with each of a first pass reference value and a first failure reference value to determine a program pass or a program failure;
generating a second failure bit accumulated value based on second memory cells of the selected memory cells when the first failure bit accumulated value is greater than the first pass reference value and is less than the first failure reference value; and
comparing the second failure bit accumulated value with each of a second pass reference value and a second failure reference value, the second pass reference value being greater than the first pass reference value, and the second failure reference value being greater than the first failure reference value.
6 . The method as claimed in claim 1 , wherein the information on the reference value includes an initial reference value and an increment of a reference value.
7 . The method as claimed in claim 6 , wherein:
the device information includes a number of program/erase cycles, and
the information on the reference value is determined based on the number of program/erase cycles.
8 . An operation method of a nonvolatile memory device, the operation method comprising:
performing a verification read on selected memory cells; and
sequentially performing, based on a pass/failure mode, a failure bit counting operation and a comparing operation to determine a program pass or a program failure, wherein:
the pass/failure mode includes one of a program failure prediction mode, a program pass prediction mode, and a program pass/failure prediction mode,
the failure bit counting operation includes generating a failure bit accumulated value,
the comparing operation includes comparing the failure bit accumulated value with a reference value, and
the reference value is changed while the failure bit counting operation is performed.
9 . The method as claimed in claim 8 , wherein the pass/failure mode is the program failure prediction mode, and
wherein the sequentially performing of the failure bit counting operation and the comparing operation includes:
generating a first failure bit accumulated value based on first memory cells of the selected memory cells;
comparing the first failure bit accumulated value with a first failure reference value to determine a program failure;
generating a second failure bit accumulated value based on second memory cells of the selected memory cells when the first failure bit accumulated value is less than the first failure reference value; and
comparing the second failure bit accumulated value with a second failure reference value to determine a program failure, the second failure reference value being greater than the first failure reference value.
10 . The method as claimed in claim 9 , wherein in the sequentially performing of the failure bit counting operation and the comparing operation, if the second failure bit accumulated value is not less than the second failure reference value, then determining the program failure, and skipping the failure bit counting operation and the comparing operation for remaining memory cells.
11 . The method as claimed in claim 8 , wherein the pass/failure mode is the program pass prediction mode, and
wherein the sequentially performing of the failure bit counting operation and the comparing operation includes:
generating a first failure bit accumulated value based on a first memory cells of the selected memory cells;
comparing the first failure bit accumulated value with a first pass reference value to determine a program pass;
generating a second failure bit accumulated value based on second memory cells of the selected memory cells when the first failure bit accumulated value is greater than the first pass reference value; and
comparing the second failure bit accumulated value with a second pass reference value to determine a program pass, the second pass reference value being greater than the first pass reference value.
12 . The method as claimed in claim 11 , wherein in the sequentially performing of the failure bit counting operation and the comparing operation, if the second failure bit accumulated value is not greater than the second pass reference value, then determining the program pass, and skipping the failure bit counting operation and the comparing operation for remaining memory cells.
13 . The method as claimed in claim 8 , wherein the pass/failure mode is the program pass/failure prediction mode, and
wherein the sequentially performing of the failure bit counting operation and the comparing operation includes:
generating a first failure bit accumulated value based on first memory cells of the selected memory cells;
comparing the first failure bit accumulated value with each of a first pass reference value and a first failure reference value to determine a program pass or a program failure;
generating a second failure bit accumulated value based on second memory cells of the selected memory cells when the first failure bit accumulated value is greater than the first pass reference value and is less than the first failure reference value; and
comparing the second failure bit accumulated value with each of a second pass reference value and a second failure reference value, the second pass reference value being greater than the first pass reference value, and the second failure reference value being greater than the first failure reference value.
14 . The method as claimed in claim 13 , wherein the sequentially performing of the failure bit counting operation and the comparing operation further includes:
determining as the program pass, and skipping the failure bit counting operation and the comparing operation for remaining memory cells when the second failure bit accumulated value is not greater than the second pass reference value; or
determining the program failure and skipping the failure bit counting operation and the comparing operation for remaining memory cells when the second failure bit accumulated value is not less than the second failure reference value.
15 . The method as claimed in claim 8 , wherein the pass/failure mode is set by an external controller.
16 . The method as claimed in claim 8 , wherein an initial value of the reference value is set by an external controller.
17 . The method as claimed in claim 8 , wherein the performing of the verification read on the selected memory cells includes applying at least one verification voltage to a selected word line connected to the selected memory cells.
18 . A nonvolatile memory device, comprising:
a memory cell array including a plurality of memory cells connected to a plurality of word lines;
a page buffer circuit connected to the memory cell array through bit lines, the page buffer circuit configured to store a verification read result at a verification read operation on selected memory cells; and
a pass/failure checker configured to sequentially perform a failure bit counting operation on the selected memory cells based on the verification read result from the page buffer circuit and a comparing operation for comparing a result of the failure bit counting operation with a reference value, and to determine program pass or program failure based on a pass/failure mode,
wherein the reference value is changed while the failure bit counting operation is performed.
19 . The nonvolatile memory device as claimed in claim 18 , wherein when the pass/failure checker determines the program pass or the program failure, the nonvolatile memory device is configured such that the pass/failure checker skips the failure bit counting operation and the comparing operation for remaining memory cells.
20 . The nonvolatile memory device as claimed in claim 18 , wherein the pass/failure mode is set by an external controller.