Method for forming FinFET with source/drain regions comprising an insulator layer
View Patent ↗An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first source/drain region in the first fin and adjacent the first gate spacer. The first source/drain region including a first insulator layer on the first fin, and a first epitaxial layer on the first insulator layer.
1 . A method comprising:
forming a fin over a substrate, the fin comprising a semiconductor material;
forming a first gate on a top surface of the fin and extending along sidewalls of the fin;
forming gate spacers along sidewalls of the first gate;
forming a first recess in the fin adjacent a first one of the gate spacers;
forming a first insulator layer in the first recess, wherein after the first insulator layer is formed, the fin being exposed at sidewalls of the first recess;
growing a first epitaxial layer from the exposed fin in the first recess; and
growing a second epitaxial layer over the first insulator layer and the first epitaxial layer in the first recess.
2 . The method of claim 1 , wherein after growing the first epitaxial layer, a gap is between the first insulator layer and the second epitaxial layer.
3 . The method of claim 2 , wherein the gap is surrounded by the first insulator layer and the first epitaxial layer.
4 . The method of claim 2 , wherein a top surface of the gap is formed by the second epitaxial layer, and wherein a bottom surface of the gap is formed by the first insulator layer.
5 . The method of claim 1 , wherein the second epitaxial layer is grown from the first epitaxial layer.
6 . The method of claim 1 , wherein the first epitaxial layer is a conformal layer.
7 . The method of claim 1 , wherein the second epitaxial layer contacts one of the gate spacers.
8 . The method of claim 1 , wherein the second epitaxial layer has a faceted top surface raised above an upper surface of the first fin.
9 . The method of claim 1 , wherein the first insulator layer is thicker at a bottom than at sidewalls of the first recess.
10 . A method comprising:
forming a first fin over a substrate;
forming an isolation region over the substrate and adjacent the first fin, the first fin having a top surface extending above a top surface of the isolation region;
forming a first gate stack over the top surface of the first fin and extending along sidewalls of the first fin and extending along the top surface of the isolation region;
forming a first gate spacer on a sidewall of the first gate stack; and
forming a first source/drain region in the first fin and adjacent the first gate spacer, wherein forming first source/drain region comprises:
forming a first insulator layer on the first fin;
forming a first epitaxial layer on the first insulator layer; and
forming a second epitaxial layer on the first insulator layer and the first epitaxial layer.
11 . The method of claim 10 , wherein the first insulator layer is thicker at a bottom than at sides of the first source/drain region.
12 . The method of claim 10 further comprising a gap between the first insulator layer and the first epitaxial layer.
13 . The method of claim 12 , wherein the gap has a planar bottom surface and a non-planar top surface.
14 . The method of claim 10 , wherein the first epitaxial layer has a faceted top surface.
15 . The method of claim 10 further comprising:
forming an etch stop layer over the first source/drain region and on a sidewall of the first gate spacer;
forming a first interlayer dielectric over the etch stop layer;
forming a second interlayer dielectric over the first interlayer dielectric; and
forming a first conductive contact extending through the first and second interlayer dielectrics and the etch stop layer, the first conductive contact being electrically coupled to the first source/drain region.
16 . The method of claim 10 , wherein the first epitaxial layer contacts the first gate spacer.
17 . The method of claim 10 , wherein the second epitaxial layer is between and contacting the first epitaxial layer and the first fin.
18 . The method of claim 10 , wherein the first insulator layer comprises silicon oxide, silicon nitride, hafnium oxide, or a combination thereof.
19 . A method comprising:
forming a fin over a substrate;
forming an isolation region over the substrate and adjacent the fin, the fin having a top surface extending above a top surface of the isolation region;
forming a first gate over the fin and the top surface of the isolation region;
forming a first source/drain region in the fin adjacent the first gate, the forming first source/drain region comprising:
forming a first insulator layer in a first recess of the fin; and
growing a first semiconductor layer over the first insulator layer and from the fin in the first recess; and
growing a second semiconductor layer over the first insulator layer and from the first semiconductor layer, the second semiconductor layer having a higher impurity concentration than the first semiconductor layer;
forming an interlayer dielectric over the first source/drain region; and
replacing the first gate with a second gate.
20 . The method of claim 19 , wherein a gap is between the first insulator layer and the second semiconductor layer, the gap being completely surrounded by the first insulator layer and the second semiconductor layer.