Integrated circuit structure with recessed self-aligned deep boundary via

1 . An integrated circuit structure, comprising:

a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures;

a plurality of trench contacts extending over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines;

a backside metal routing layer extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts; and

a conductive structure coupling the backside metal routing layer to one of the one or more of the plurality of trench contacts, the conductive structure comprising a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

2 . The integrated circuit structure of claim 1 , wherein the backside metal routing layer is a backside power delivery line.

3 . The integrated circuit structure of claim 1 , wherein the conductive structure is a recessed boundary deep via structure.

4 . The integrated circuit structure of claim 1 , wherein the pillar portion of the conductive structure extends between a pair of N-type source or drain structures of plurality of source or drain structures or extends between a pair of P-type source or drain structures of plurality of source or drain structures.

5 . The integrated circuit structure of claim 1 , further comprising a dielectric liner along sides of the pillar portion and the line portion of the conductive structure.

6 . An integrated circuit structure, comprising:

a plurality of gate lines extending over a plurality of semiconductor fin structures;

a plurality of trench contacts extending over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines;

a backside metal routing layer extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts; and

a conductive structure coupling the backside metal routing layer to one of the one or more of the plurality of trench contacts, the conductive structure comprising a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

7 . The integrated circuit structure of claim 6 , wherein the backside metal routing layer is a backside power delivery line.

8 . The integrated circuit structure of claim 6 , wherein the conductive structure is a recessed boundary deep via structure.

9 . The integrated circuit structure of claim 6 , wherein the pillar portion of the conductive structure extends between a pair of N-type source or drain structures of plurality of source or drain structures or extends between a pair of P-type source or drain structures of plurality of source or drain structures.

10 . The integrated circuit structure of claim 6 , further comprising a dielectric liner along sides of the pillar portion and the line portion of the conductive structure.

11 . A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures;

a plurality of trench contacts extending over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines;

a backside metal routing layer extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts; and

a conductive structure coupling the backside metal routing layer to one of the one or more of the plurality of trench contacts, the conductive structure comprising a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

12 . The computing device of claim 11 , further comprising:

a memory coupled to the board.

13 . The computing device of claim 11 , further comprising:

a communication chip coupled to the board.

14 . The computing device of claim 11 , further comprising:

a camera coupled to the board.

15 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

16 . A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

a plurality of gate lines extending over a plurality of semiconductor fin structures;

a plurality of trench contacts extending over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines;

a backside metal routing layer extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts; and

a conductive structure coupling the backside metal routing layer to one of the one or more of the plurality of trench contacts, the conductive structure comprising a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

17 . The computing device of claim 16 , further comprising:

a memory coupled to the board.

18 . The computing device of claim 16 , further comprising:

a communication chip coupled to the board.

19 . The computing device of claim 16 , further comprising:

a camera coupled to the board.

20 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.