IP Library › Granted Patent US 12,469,792
Granted Patent B2
US 12,469,792 · App. 17/876,228 · Granted Nov 11, 2025

Semiconductor device

Inventor: Makoto Isozaki (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L23/5386H01L23/142H01L23/367H01L24/45H01L24/48H01L24/85H01L2224/45124H01L2224/45139H01L2224/45144H01L2224/45147H01L2224/48137H01L2224/48225H01L2224/85424H01L2224/85447
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,469,792
App. No.
17/876,228
Granted
Nov 11, 2025
Kind
B2
Abstract

A semiconductor device, including an insulated circuit substrate that has a base plate, a resin layer disposed on a front surface of the base plate, and a circuit pattern disposed on a front surface of the resin layer; and a semiconductor chip that is rectangular in a plan view of the semiconductor device and is bonded to a front surface of the circuit pattern in such a manner that a side edge of the semiconductor chip is spaced inwardly from an outer peripheral edge of the circuit pattern by at least a predetermined distance. Both the predetermined distance and a thickness of the circuit pattern are greater than or equal to 0.1 of a length of one side of the semiconductor chip.

Claims (29)

1 . A semiconductor device, comprising:

an insulated circuit substrate, including

a base plate,

a resin layer disposed on a front surface of the base plate, and

a circuit pattern disposed on a front surface of the resin layer; and

a semiconductor chip that is rectangular in a plan view of the semiconductor device and is bonded to a front surface of the circuit pattern in such a manner that a side edge of the semiconductor chip is spaced inwardly from an outer peripheral edge of the circuit pattern by at least a predetermined distance, wherein

both the predetermined distance and a thickness of the circuit pattern are greater than or equal to 0.1 of a length of one side of the semiconductor chip, and

in a depth direction of the semiconductor device, a bottommost portion of the circuit pattern is closer to the base plate than is a topmost portion of the resin layer, and a topmost portion of the circuit pattern is farther from the base plate than is the topmost portion of the resin layer.

2 . The semiconductor device according to claim 1 , further comprising

another semiconductor chip bonded to the front surface of the circuit pattern, the another semiconductor chip being adjacent to the semiconductor chip in a side view of the semiconductor device,

wherein another side edge of the semiconductor chip, and a side edge of the another semiconductor chip adjacent to said another side edge, have a gap therebetween in the side view, the gap being greater than or equal to twice the predetermined distance.

3 . The semiconductor device according to claim 2 , further comprising a wiring member bonded to the front surface of the circuit pattern in the gap.

4 . The semiconductor device according to claim 2 , further comprising a groove formed in the gap in the front surface of the circuit pattern, the groove being parallel to the semiconductor chip and the another semiconductor chip in the plan view.

5 . The semiconductor device according to claim 4 , wherein

the circuit pattern has a heat spreading area that is an area in which heat generated by the semiconductor chip is spreadable as the heat moves toward the resin layer, and

the groove has such a depth that the groove does not reach an outermost edge of the heat spreading area, the outermost edge being beveled at 45 degrees in the side view.

6 . The semiconductor device according to claim 1 , wherein the circuit pattern is embedded in the resin layer in such a manner that the front surface of the circuit pattern is flush with the front surface of the resin layer.

7 . The semiconductor device according to claim 1 , wherein

the circuit pattern has a heat spreading area that is an area in which heat generated by the semiconductor chip is spreadable as the heat moves toward the resin layer, an outermost edge of the heat spreading area being beveled at 45 degrees in a side view of the semiconductor device,

the circuit pattern is chamfered, and

the outermost edge of the heat spreading area is within the chamfered circuit pattern.

8 . The semiconductor device according to claim 1 , wherein the circuit pattern has a sag at a first side thereof facing the resin layer, and has a burr at a second side thereof that is a side of the front surface of the circuit pattern and opposite to the first side.

9 . The semiconductor device according to claim 1 , further comprising

a non-disposition circuit pattern disposed together with the circuit pattern on the front surface of the resin layer, the non-disposition circuit pattern being a pattern on which the semiconductor chip is not disposed,

wherein the non-disposition circuit pattern is thinner than the circuit pattern.

10 . The semiconductor device according to claim 9 , wherein

the semiconductor chip has a control electrode, and

the non-disposition circuit pattern is a control circuit pattern that is electrically connected to the control electrode of the semiconductor chip.

11 . The semiconductor device according to claim 1 , wherein the length of the one side of the semiconductor chip is less than or equal to 5.5 mm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2022
From: ISOZAKI, MAKOTO
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 060661/0445 →
Priority Claims (1)
JP 2020-144178 · Aug 28, 2020 · national
Continuity (2)
Continuation PCTJP2021024996 · Jul 1, 2021
Related Publication 20220367372A1 · Nov 17, 2022
References Cited (29)
US 9627302B2 · Ichikawa et al. · 2017 [cited by applicant]
US 20060258055A1 · Okamoto · 2006 [cited by examiner]
US 20100041228A1 · Okamoto · 2010 [cited by applicant]
US 20120134115A1 · Schulz-Harder et al. · 2012 [cited by applicant]
US 20130187190A1 · Muramatsu et al. · 2013 [cited by applicant]
US 20150035138A1 · Miyamoto · 2015 [cited by examiner]
US 20160233151A1 · Ichikawa · 2016 [cited by examiner]
US 20170229389A1 · Katsuki · 2017 [cited by applicant]
US 20180145007A1 · Hatano et al. · 2018 [cited by applicant]
DE 112014006142T5 · 2016 [cited by applicant]
JP H06164090A · 1994 [cited by applicant]
JP H106350212A · 1994 [cited by applicant]
JP H11186679A · 1999 [cited by applicant]
JP 2002217508A · 2002 [cited by applicant]
JP 2006319146A · 2006 [cited by applicant]
JP 2010056576A · 2010 [cited by examiner]
JP 2010103311A · 2010 [cited by applicant]
JP 2012531728A · 2012 [cited by applicant]
JP 2013153067A · 2013 [cited by applicant]
JP 2013207226A · 2013 [cited by applicant]
JP 2014022579A · 2014 [cited by examiner]
JP 2017139406A · 2017 [cited by applicant]
JP 2017199830A · 2017 [cited by applicant]
JP 2019071399A · 2019 [cited by applicant]
JP 2019169540A · 2019 [cited by applicant]
International Search Report for PCT/JP2021/024996, mailed on Sep. 28, 2021. [cited by applicant]
Written Opinion for PCT/JP2021/024996, mailed on Sep. 28, 2021. [cited by applicant]
German Office action dated Oct. 1, 2024, in the counterpart German patent application No. 11 2021 000 290.2. [cited by applicant]
Japanese Office Action issued on Apr. 15, 2025, for corresponding Japanese Patent Application No. 2023-194122. [cited by applicant]