Method for manufacturing semiconductor package with connection structures including via groups
A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.
1 . A package comprising:
an Under-Bump Metallurgy (UBM);
a top via underlying and electrically coupling to the UBM;
a first conductive pad underlying and electrically coupling to the top via;
a first via group underlying and contacting the first conductive pad, wherein the first via group comprises a first plurality of vias, and the first via group has a first contour area;
a second conductive pad underlying and electrically coupling to the first via group;
a second via group underlying and contacting the second conductive pad, wherein the second via group comprises a second plurality of vias, and the second via group has a second contour area overlapped by the first contour area; and
a die underlying the second via group, wherein the die comprises a discrete via electrically coupling to the second via group, and wherein the first contour area and the second contour area overlap the discrete via.
2 . The package of claim 1 , wherein each via in the first plurality of vias is vertically misaligned with each via in the second plurality of vias.
3 . The package of claim 2 , wherein in a top view of the package, the first plurality of vias are aligned to a first circle, and the second plurality of vias are aligned to a second circle.
4 . The package of claim 3 , wherein the first contour area overlaps an entirety of the second contour area.
5 . The package of claim 1 , wherein the first contour area is larger than the second contour area.
6 . The package of claim 1 further comprising:
a third via group underlying and electrically coupling to the second via group, wherein the third via group is over and electrically coupled to the discrete via, wherein the third via group comprises a third plurality of vias, and wherein the third via group has a third contour area overlapped by the second contour area.
7 . The package of claim 6 , wherein the third plurality of vias have bottoms physically contacting a same top surface of the discrete via in the die.
8 . The package of claim 1 , wherein neighboring vias among the first plurality of vias have a uniform pitch.
9 . The package of claim 1 , wherein the discrete via is overlapped by the UBM.
10 . The package of claim 1 , wherein the first plurality of vias are allocated symmetrical to a vertical center line, and the second plurality of vias are allocated symmetrical to the vertical center line.
11 . The package of claim 1 further comprising a solder region over and contacting the UBM.
12 . A package comprising:
a top conductive feature;
a plurality of metal pads underlying and electrically coupling to the top conductive feature, with upper pads in the plurality of metal pads overlapping lower pads in the plurality of metal pads;
a plurality of via groups, each connecting an upper pad among the plurality of metal pads to a respective lower pad among the plurality of metal pads, wherein each of the plurality of via groups comprises a plurality of vias having a contour area, and wherein the contour area of each of the plurality of via groups is overlapped at least partially by the top conductive feature, and wherein upper groups among the plurality of via groups have contour areas larger than respective lower groups among the plurality of via groups; and
a device die comprising a discrete conductive feature, wherein the discrete conductive feature is overlapped by, and is electrically coupled to, the top conductive feature.
13 . The package of claim 12 further comprising:
a solder region; and
a package substrate bonding to the top conductive feature through the solder region.
14 . The package of claim 12 , wherein the plurality of vias of one of the plurality of via groups are distributed aligning to a circle.
15 . The package of claim 12 , wherein vias in each of the plurality of via groups are symmetric to a vertical center line.
16 . The package of claim 12 , wherein the upper pads in the plurality of metal pads are larger than the respective lower pads in the plurality of metal pads.
17 . A package comprising:
a device die comprising a conductive feature;
an encapsulant encapsulating the device die therein;
a first plurality of vias over and electrically coupling to the device die, wherein the first plurality of vias encircle a first area, and are aligned to a first circle;
a first metal pad over and physically contacting top surfaces of the first plurality of vias;
a second plurality of vias over and physically contacting a top surface of the first metal pad, wherein the second plurality of vias are aligned to a second circle, and wherein the second circle overlaps the first circle;
a second metal pad over and physically contacting top surfaces of the second plurality of vias; and
an Under-Bump-Metallurgy (UBM) over and electrically coupling to the conductive feature of the device die through the first plurality of vias and the second plurality of vias, wherein the UBM, the first circle, and the second circle at least partially overlap the conductive feature.
18 . The package of claim 17 , wherein the first plurality of vias encircle a first center, and the second plurality of vias encircle a second center, and the second center is vertically aligned to the first center, and wherein each of the first plurality of vias is vertically offset from each of the second plurality of vias.
19 . The package of claim 17 , wherein the first plurality of vias have a first contour area, and the second plurality of vias have a second contour area different from the first contour area.
20 . The package of claim 19 , wherein the second contour area is greater than the first contour area.