Semiconductor packages and methods of forming the same

1. A semiconductor package, comprising:

a chip;

a redistribution circuit structure, disposed over and electrically connected to the chip and comprising a topmost conductive pattern;

a under-ball metallurgy (UBM) pattern disposed over and electrically connected to the topmost conductive pattern, wherein the UBM pattern comprises a set of vias and a pad on the set of vias, wherein the vias are arranged in an array and electrically connected to the pad and the topmost conductive pattern;

a passive component mounted to the redistribution circuit structure through the UBM pattern; and

a solder region between the UBM pattern and the passive component.

2. The semiconductor package of claim 1 , wherein the vias are overlapped with the topmost conductive pattern.

3. The semiconductor package of claim 1 , wherein shapes of the vias comprise circle or regular polygon.

4. A semiconductor package, comprising:

a chip;

a conductive pattern disposed over and electrically connected to the chip;

a dielectric layer, disposed over the conductive pattern and comprising a set of openings to expose the conductive pattern; and

a under-ball metallurgy (UBM) pattern, comprising a set of vias in the set of openings and a pad on the set of vias, wherein the pad is electrically connected to the conductive pattern through the set of vias, and a ratio of a total height (H) of the dielectric layer and the pad to a bottom critical dimension (BCD) of the via is equal to or larger than 0.2 (H/BCD=0.2 or H/BCD>0.2).

5. The semiconductor package of claim 4 , wherein the vias are overlapped with the conductive pattern.

6. The semiconductor package of claim 4 , wherein a top surface of the pad comprises at least one convex portion.

7. The semiconductor package of claim 6 , wherein a height of the convex portion is smaller than 1 μm.

8. The semiconductor package of claim 4 , wherein a top surface of the pad comprises at least one concave portion.

9. The semiconductor package of claim 8 , wherein a depth of the concave portion is smaller than 1 μm.

10. The semiconductor package of claim 4 , wherein the UBM pattern comprises bright copper.

11. The semiconductor package of claim 4 , wherein shapes of the vias comprise circle or regular polygon.

12. The semiconductor package of claim 4 further comprising a passive component mounted to the redistribution circuit structure through the UBM pattern.

13. The semiconductor package of claim 12 further comprising a solder region between the UBM pattern and the passive component.

14. The semiconductor package of claim 1 , wherein a top surface of the pad comprises at least one convex portion.

15. The semiconductor package of claim 1 , wherein a top surface of the pad comprises at least one concave portion.

16. The semiconductor package of claim 1 , wherein the UBM pattern comprises bright copper.

17. A method of forming a semiconductor package, comprising:

forming a conductive pattern of a redistribution circuit structure over a chip to electrically connect the chip;

forming a dielectric layer comprising a set of openings over the conductive pattern, wherein the set of openings exposes the conductive pattern; and

forming a under-ball metallurgy (UBM) pattern to electrically connect the conductive pattern, wherein the UBM pattern comprises a set of vias in the set of openings and a pad on the set of vias over the dielectric layer, and a ratio of a total height (H) of the dielectric layer and the pad to a bottom critical dimension (BCD) of the via is equal to or larger than 0.2 (H/BCD=0.2 or H/BCD>0.2).

18. The method of claim 17 , wherein a forming method of the UBM pattern comprises bright copper plating.

19. The method of claim 17 , wherein the openings are arranged in an array, and the vias are arranged in an array correspondingly.

20. The method of claim 17 , further comprising bonding a passive component to the conductive pattern through a solder region therebetween.