Deadlock prevention of switch memory overflow
Example embodiments disclose a method for avoiding deadlock in a network includes generating a finite state machine indicating possible routing decisions of incoming packets for a plurality of switches, analyzing the finite state machine, determining at least one memory overflow state based on the analyzing, generating at least one anti-deadlock rule in response to determining the at least one memory overflow state, and transmitting the at least one anti-deadlock rule to the plurality of switches.
1 . A method for avoiding deadlock in a network, the method comprising:
generating, in response to a first switch updating a routing table of the first switch, a finite state machine indicating possible routing decisions of incoming packets for a plurality of switches including first switch;
analyzing the finite state machine;
determining at least one memory overflow state of a buffer memory of at least one switch of the plurality of switches based on the analyzing;
generating at least one anti-deadlock rule in response to determining the at least one memory overflow state; and
transmitting the at least one anti-deadlock rule to the plurality of switches.
2 . The method of claim 1 , wherein the at least one memory overflow state indicates a transition between a state, in the finite state machine, of a second switch, of the plurality of switches, with a memory occupancy that is larger than an available memory space of the second switch.
3 . The method of claim 1 , wherein the transmitting transmits the at least one anti-deadlock rule to the plurality of switches for use in routing the incoming packets at the plurality of switches.
4 . The method of claim 1 , further comprising:
analyzing the finite state machine to determine a deadlock path within the network based on the at least one memory overflow state,
wherein the generating the at least one anti-deadlock rule includes generating the at least one anti-deadlock rule based on the deadlock path.
5 . The method of claim 4 , wherein the generating the at least one anti-deadlock rule comprises:
generating, for switches along the deadlock path, at least one forbidden routing rule, the forbidden routing rule indicating
a set of memory buffers of the switches along the deadlock path associated with the forbidden routing rule, and
a list of forbidden routing rules local to a switch of the plurality of switches.
6 . The method of claim 5 ,
wherein the analyzing includes noting a plurality of buffer allocations, in the finite state machine, between states of the plurality of switches, and
wherein the generating the at least one anti-deadlock rule generates the at least one anti-deadlock rule based on a set of memory buffers, of the plurality of switches along the deadlock path, based on buffer allocations, of the plurality of buffer allocations, along the deadlock path.
7 . The method of claim 1 , wherein the generating the finite state machine comprises:
generating a plurality of individual routing rule finite state machines, each individual routing rule finite state machine of the plurality of individual routing rule finite state machines describing switch memory evolution, of the buffer memory of the plurality of switches, as a consequence of an application of a routing rule; and
combining the plurality of individual routing rule finite state machines to generate the finite state machine.
8 . The method of claim 1 , wherein the finite state machine describes all possible evolutions of buffer memories of the plurality of switches according to routing decisions that can be taken by the plurality of switches on incoming packets.
9 . An apparatus for avoiding deadlock in a network, the apparatus comprising:
a memory; and
processing circuitry configured to cause the apparatus to
generate, in response to a first switch updating a routing table of the first switch, a finite state machine indicating possible routing decisions of incoming packets for a plurality of switches including the first switch,
analyze the finite state machine,
determine at least one memory overflow state of a buffer memory of at least one switch of the plurality of switches based on the analysis,
generate at least one anti-deadlock rule in response to determining the at least one memory overflow state, and
transmit the at least one anti-deadlock rule to the plurality of switches.
10 . The apparatus of claim 9 , wherein the at least one memory overflow state indicates a transition between a state, in the finite state machine, of a second switch, of the plurality of switches, with a memory occupancy that is larger than an available memory space of the second switch.
11 . The apparatus of claim 9 , wherein the processing circuitry is further configured to cause the apparatus to transmit the at least one anti-deadlock rule to the plurality of switches for use in routing the incoming packets at the plurality of switches.
12 . The apparatus of claim 9 , wherein the processing circuitry is further configured to cause the apparatus to:
analyze the finite state machine to determine a deadlock path within the network based on the at least one memory overflow state; and
generate the at least one anti-deadlock rule based on the deadlock path.
13 . The apparatus of claim 12 , wherein the processing circuitry is further configured to cause the apparatus to generate the anti-deadlock rule by generating, for switches along the deadlock path, at least one forbidden routing rule, the forbidden routing rule indicating
a set of memory buffers of the switches along the deadlock path associated with the forbidden routing rule, and
a list of forbidden routing rules local to a switch of the plurality of switches.
14 . The apparatus of claim 13 , wherein the processing circuitry is further configured to cause the apparatus to
note a plurality of buffer allocations, in the finite state machine, between states of the plurality of switches during the analysis of the finite state machine, and
generate the at least one anti-deadlock rule based on a set of memory buffers, of the plurality of switches along the deadlock path, based on buffer allocations, of the plurality of buffer allocations, along the deadlock path.
15 . The apparatus of claim 9 , wherein the processing circuitry is further configured to cause the apparatus to:
generate a plurality of individual routing rule finite state machines, each individual routing rule finite state machine of the plurality of individual routing rule finite state machines describing switch memory evolution, of the buffer memory of the plurality of switches, as a consequence of an application of a routing rule; and
generate the finite state machine by combining the plurality of individual routing rule finite state machines.
16 . A method for avoiding deadlock in a network, the method comprising:
routing, by a first switch of a plurality of switches, a data packet according to at least one anti-deadlock rule, the at least one anti-deadlock rule based on a deadlock path within the network, the deadlock path in the network being determined by an analysis of a finite state machine indicating at least one memory overflow state of a buffer memory of at least one switch of the plurality of switches, the finite state machine having been generated in response to a second switch of the plurality of switches updating a routing table of the second switch.
17 . The method of claim 1 , wherein
the analyzing analyzes the finite state machine to determine at least one deadlock path within the network, and
the generating the at least one anti-deadlock rule includes generating at least one respective anti-deadlock rule based on each deadlock path of the at least one deadlock path.