Method and apparatus to perform operations on multiple segments of a data packet in a network interface controller
A stacked memory such as a high bandwidth memory (HBM) with a wide data path is used by a streaming pipeline in a network interface controller to buffer segments of a data packet to allow the network interface controller to perform operations on the packet payload. The headers and packet payload can be scanned and classified concurrently with the buffered payload parsed in parallel.
1 . A computing device comprising:
a package comprising:
a stacked High Bandwidth Memory (HBM)-consistent memory; and
a network interface controller (NIC) communicatively coupled to the memory, the NIC comprising:
an ingress buffer;
a payload buffer circuitry;
a host interface; and
packet processing circuitry to:
inspect a first segment of a data packet to determine whether to stream a second segment of the data packet or to store the first segment and the second segment of the data packet in the memory to perform operations on the first segment and the second segment of the data packet, and based on a determination to stream the second segment of the data packet, the packet processing circuitry is to copy the second segment of the data packet from port circuitry via the ingress buffer and the payload buffer circuitry to the host interface.
2 . The computing device of claim 1 , wherein the NIC is coupled to the memory by a wide data path that is 1024 bits in width.
3 . The computing device of claim 1 , wherein the first segment of the data packet is received by port circuitry in the NIC.
4 . The computing device of claim 1 , wherein the first segment of the data packet is received by host interface circuitry in the NIC.
5 . The computing device of claim 1 , wherein the package comprises a multi-chip package and wherein a first die includes the memory and a second die includes the NIC and a multi-chip package includes the first die and the second die.
6 . The computing device of claim 1 , wherein if the first segment indicates that the operations are not to be performed on the data packet, the second segment of the data packet is streamed directly to port circuitry or host interface circuitry in the NIC.
7 . The computing device of claim 1 , wherein:
based on a determination to store the first segment and the second segment of the data packet in the HBM-consistent memory to perform operations on the first segment and the second segment of the data packet, the packet processing circuitry is to: copy the second segment to the HBM-consistent memory, and if the second segment is a last segment of the data packet, copy the second segment to the packet processing circuitry to process the second segment, store the processed second segment in the payload buffer circuitry, and copy the processed second segment to the host interface circuitry.
8 . The computing device of claim 1 , wherein the first segment comprises a header and the second segment comprises data.
9 . The computing device of claim 1 , wherein:
the packet processing circuitry is to:
inspect a third segment of the data packet to determine if the third segment is a last segment of the data packet and
based on a determination to store the first segment and the second segment of the data packet in the HBM-consistent memory to perform operations on the first segment and the second segment of the data packet, copy the third segment of the data packet to the HBM-consistent memory, and if the third segment is a last segment of the data packet, copy the third segment to the packet processing circuitry to process the third segment, store the processed third segment in the payload buffer circuitry, and copy the processed third segment to the host interface circuitry.
10 . A system comprising:
a multi-chip package comprising:
a stacked High Bandwidth Memory (HBM)-consistent memory; and
a network interface controller (NIC) communicatively coupled to the memory, the NIC comprising:
an ingress buffer;
a payload buffer circuitry;
a host interface; and
packet processing circuitry to inspect a first segment of a data packet to determine whether to stream a second segment of the data packet or to store the first segment and the second segment of the data packet in the memory to perform operations on the first segment and the second segment of the data packet, and based on a determination to stream the second segment of the data packet, the packet processing circuitry is to copy the second segment of the data packet from port circuitry via an ingress buffer and a payload buffer circuitry to a host interface circuitry.
11 . The system of claim 10 , wherein the NIC is coupled to the memory by a wide data path that is 1024 bits in width.
12 . The system of claim 10 , wherein the first segment of the data packet is received by port circuitry in the NIC.
13 . The system of claim 10 , wherein the first segment of the data packet is received by the host interface circuitry.
14 . The system of claim 10 , wherein if the first segment indicates that the operations are not to be performed on the data packet, the second segment of the data packet are streamed directly to port circuitry or host interface circuitry.
15 . A method comprising:
receiving, by packet processing circuitry in a network interface controller (NIC) a first segment of a data packet, wherein a multi-chip package comprises the NIC and a stacked High Bandwidth Memory (HBM)-consistent memory device and the NIC comprises an ingress buffer, a payload buffer circuitry, a host interface, and the packet processing circuitry; and
determining, by the packet processing circuitry, based on an inspection of the first segment of the data packet whether to stream a second segment of the data packet or to store the first segment and the second segment of the data packet in a stacked High Bandwidth Memory (HBM) memory communicatively coupled to the network interface controller to perform operations on the first segment and the second segment of the data packet.
16 . The method of claim 15 , wherein the NIC is coupled to the memory by a wide data path that is 1024 bits in width.
17 . The method of claim 15 , wherein the first segment of the data packet is received by port circuitry in the NIC.
18 . The method of claim 15 , wherein the first segment of the data packet is received by host interface circuitry in the NIC.
19 . The method of claim 15 , wherein a first die includes the stacked HBM memory and a second die includes the NIC and a multi-chip package includes the first die and the second die.
20 . The method of claim 15 , wherein if the first segment indicates that the operations are not to be performed on the data packet, the second segment of the data packet are streamed directly to port circuitry or host interface circuitry in the NIC.