Two port SRAM device using forked nanosheet FETs
A semiconductor storage device including a two-port SRAM cell, in which nanosheets 21 to 24 are formed in line in this order in the X direction, and nanosheets 25 to 28 are formed in line in this order in the X direction. Faces of the nanosheets 21, 23, 25 , and 27 on the first side in the X direction are exposed from gate interconnects 30, 33, 35 , and 36 , respectively. Faces of the nanosheets 22, 24, 26 , and 28 on the second side in the X direction are exposed from gate interconnects 33, 34, 36 , and 39 , respectively.
1 . A semiconductor storage device including a two-port SRAM cell, the two-port SRAM cell comprising:
a first transistor connected to a first power supply supplying a first voltage at one of its nodes, to a first node at the other node, and to a second node at its gate;
a second transistor connected to the first power supply at one of its nodes, to the second node at the other node, and to the first node at its gate;
a third transistor connected to a first bit line at one of its nodes, to the first node at the other node, and to a first word line at its gate;
a fourth transistor connected to a second bit line at one of its nodes, to the second node at the other node, and to the first word line at its gate, the first bit line and the second bit line constituting a first complementary bit line pair;
a fifth transistor connected to a third bit line at one of its nodes, to the first node at the other node, and to a second word line at its gate;
a sixth transistor connected to a fourth bit line at one of its nodes, to the second node at the other node, and to the second word line at its gate, the third bit line and the fourth bit line constituting a second complementary bit line pair;
a seventh transistor connected to the first node at one of its nodes, to a second power supply supplying a second voltage different from the first voltage at the other node, and to the second node at its gate; and
an eighth transistor connected to the second node at one of its nodes, to the second power supply at the other node, and to the first node at its gate,
wherein
the first to sixth transistors respectively include:
first to sixth nanosheets extending in a first direction, and
first to sixth gate interconnects surrounding the first to sixth nanosheets, respectively, in a second direction vertical to the first direction and in a third direction perpendicular to the first and second directions,
the seventh transistor includes:
seventh and eighth nanosheets extending in the first direction, and
seventh and eighth gate interconnects surrounding the seventh and eighth nanosheets, respectively, in the second and third directions,
the eighth transistor includes:
ninth and tenth nanosheets extending in the first direction, and
ninth and tenth gate interconnects surrounding the ninth and tenth nanosheets, respectively, in the second and third directions,
the sixth, fifth, second, ninth, and tenth nanosheets are formed in line in this order in the second direction,
the seventh, eighth, first, fourth, and third nanosheets are formed in line in this order in the second direction,
faces of the second, sixth, eighth, and tenth nanosheets on a first side as one of the opposite sides in the second direction are exposed from the second, sixth, eighth, and tenth gate interconnects, respectively,
faces of the first, third, seventh, and ninth nanosheets on a second side as the other side in the second direction are exposed from the first, third, seventh, and ninth gate interconnects, respectively,
a face of the fourth nanosheet on either the first or second side is exposed from the fourth gate interconnect, and
a face of the fifth nanosheet on either the first or second side is exposed from the fifth gate interconnect.
2 . The semiconductor storage device of claim 1 , wherein
the third nanosheet is formed close to a cell boundary of the two-port SRAM cell on the second side,
the sixth nanosheet is formed close to a cell boundary of the two-port SRAM cell on the first side,
the first side is the side on which the tenth nanosheet is opposed to the ninth nanosheet and the side on which the eighth nanosheet is opposed to the seventh nanosheet, and
the second side is the side on which the ninth nanosheet is opposed to the tenth nanosheet and the side on which the seventh nanosheet is opposed to the eighth nanosheet.
3 . The semiconductor storage device of claim 2 , wherein
the fifth and seventh nanosheets are formed side by side in the first direction,
the fourth and tenth nanosheets are formed side by side in the first direction,
a face of the fourth nanosheet on the first side is exposed from the fourth gate interconnect, and
a face of the fifth nanosheet on the second side is exposed from the fifth gate interconnect.
4 . The semiconductor storage device of claim 2 , wherein
the fifth and eighth nanosheets are formed side by side in the first direction,
the fourth and ninth nanosheets are formed side by side in the first direction,
a face of the fourth nanosheet on the second side is exposed from the fourth gate interconnect, and
a face of the fifth nanosheet on the first side is exposed from the fifth gate interconnect.
5 . The semiconductor storage device of claim 1 , wherein
the first side is the side on which the second nanosheet is opposed to the ninth nanosheet, and the side on which the eight nanosheet is opposed to the first nanosheet, and
the second side is the side on which the ninth nanosheet is opposed to the second nanosheet, and the side on which the first nanosheet is opposed to the eighth nanosheet.
6 . The semiconductor storage device of claim 5 , wherein
the fifth and seventh nanosheets are formed side by side in the first direction,
the fourth and tenth nanosheets are formed side by side in the first direction,
a face of the fourth nanosheet on the first side is exposed from the fourth gate interconnect,
a face of the fifth nanosheet on the second side is exposed from the fifth gate interconnect,
the first side is the side on which the sixth nanosheet is opposed to the fifth nanosheet, and the side on which the fourth nanosheet is opposed to the third nanosheet, and
the second side is the side on which the fifth nanosheet is opposed to the sixth nanosheet, and the side on which the third nanosheet is opposed to the fourth nanosheet.
7 . The semiconductor storage device of claim 5 , wherein
the fifth and eighth nanosheets are formed side by side in the first direction,
the fourth and ninth nanosheets are formed side by side in the first direction,
a face of the fourth nanosheet on the second side is exposed from the fourth gate interconnect, and
a face of the fifth nanosheet on the first side is exposed from the fifth gate interconnect.
8 . The semiconductor storage device of claim 1 , wherein
the two-port SRAM cell further comprises:
first and second power lines extending in the first direction and supplying the second voltage;
a first interconnect extending in the first direction, which is to be the first bit line;
a second interconnect extending in the first direction, which is to be the second bit line;
a third interconnect extending in the first direction, which is to be the third bit line; and
a fourth interconnect extending in the first direction, which is to be the fourth bit line,
the first and second power lines and the first to fourth interconnects are formed in a same interconnect layer above the first to tenth transistors,
the first power line is formed between the first interconnect and the second interconnect, and
the second power line is formed between the third interconnect and the fourth interconnect.
9 . A semiconductor storage device including a two-port SRAM cell, the two-port SRAM cell comprising:
a first transistor connected to a first power supply supplying a first voltage at one of its nodes, to a first node at the other node, and to a second node at its gate;
a second transistor connected to the first power supply at one of its nodes, to the second node at the other node, and to the first node at its gate;
a third transistor connected to a first bit line at one of its nodes, to the first node at the other node, and to a first word line at its gate;
a fourth transistor connected to a second bit line at one of its nodes, to the second node at the other node, and to the first word line at its gate, the first bit line and the second bit line constituting a first complementary bit line pair;
a fifth transistor connected to a third bit line at one of its nodes, to the first node at the other node, and to a second word line at its gate;
a sixth transistor connected to a fourth bit line at one of its nodes, to the second node at the other node, and to the second word line at its gate, the third bit line and the fourth bit line constituting a second complementary bit line pair;
a seventh transistor connected to the first node at one of its nodes, to a second power supply supplying a second voltage different from the first voltage at the other node, and to the second node at its gate; and
an eighth transistor connected to the second node at one of its nodes, to the second power supply at the other node, and to the first node at its gate,
wherein
the first to sixth transistors respectively include:
first to sixth nanosheets extending in a first direction, and
first to sixth gate interconnects surrounding the first to sixth nanosheets, respectively, in a second direction vertical to the first direction and in a third direction perpendicular to the first and second directions,
the seventh transistor includes:
seventh and eighth nanosheets extending in the first direction, and
seventh and eighth gate interconnects surrounding the seventh and eighth nanosheets, respectively, in the second and third directions,
the eighth transistor includes:
ninth and tenth nanosheets extending in the first direction, and
ninth and tenth gate interconnects surrounding the ninth and tenth nanosheets, respectively, in the second and third directions,
the fifth, third, second, ninth, and tenth nanosheets are formed in line in this order in the second direction,
the seventh, eighth, first, sixth, and fourth nanosheets are formed in line in this order in the second direction,
faces of the first, fifth, sixth, seventh, and ninth nanosheets on a first side as one of the opposite sides in the second direction are exposed from the first, fifth, sixth, seventh, and ninth gate interconnects, respectively, and
faces of the second, third, fourth, eighth, and tenth nanosheets on a second side as the other side in the second direction are exposed from the second, third, fourth, eighth, and tenth gate interconnects, respectively.
10 . The semiconductor storage device of claim 9 , wherein
the first side is the side on which the ninth nanosheet is opposed to the second nanosheet and the side on which the first nanosheet is opposed to the eighth nanosheet,
the second side is the side on which the second nanosheet is opposed to the ninth nanosheet and the side on which the eighth nanosheet is opposed to the first nanosheet,
the fifth and seventh nanosheets are formed close to a cell boundary of the two-port SRAM cell on the first side, and
the fourth and tenth nanosheets are formed close to a cell boundary of the two-port SRAM cell on the second side.
11 . The semiconductor storage device of claim 9 , wherein
the first side is the side on which the fifth nanosheet is opposed to the third nanosheet and the side on which the ninth nanosheet is opposed to the tenth nanosheet, the side on which the seventh nanosheet is opposed to the eighth nanosheet, and the side on which the sixth nanosheet is opposed to the fourth nanosheet, and
the second side is the side on which the third nanosheet is opposed to the fifth nanosheet, the side on which the tenth nanosheet is opposed to the ninth nanosheet, the side on which the eighth nanosheet is opposed to the seventh nanosheet, and the side on which the fourth nanosheet is opposed to the sixth nanosheet.
12 . The semiconductor storage device of claim 9 , wherein
the two-port SRAM cell further comprises:
first and second power lines extending in the first direction and supplying the second voltage;
a first interconnect extending in the first direction, which is to be the first bit line;
a second interconnect extending in the first direction, which is to be the second bit line;
a third interconnect extending in the first direction, which is to be the third bit line; and
a fourth interconnect extending in the first direction, which is to be the fourth bit line,
the first and second power lines and the first to fourth interconnects are formed in a same interconnect layer above the first to tenth transistors,
the first power line is formed between the first interconnect and the third interconnect, and
the second power line is formed between the second interconnect and the fourth interconnect.