Integrated circuit structures having ultra-high conductivity global routing
Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.
1 . An integrated circuit structure, comprising:
a device layer having a plurality of transistors; and
a plurality of metallization layers above the plurality of transistors of the device layer, wherein one or more of the metal layers comprises a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.
2 . The integrated circuit structure of claim 1 , wherein the material comprises Nb and N, Nb and Sn, or Nb and Ge.
3 . The integrated circuit structure of claim 1 , wherein the material comprises Cu and La and Ba and O, or Cu and La and Sr and O, or Cu and Y and Ba and O.
4 . The integrated circuit structure of claim 1 , wherein the material comprises Cs and Rb and C, or Cs and C.
5 . The integrated circuit structure of claim 1 , wherein the plurality of transistors is a plurality of nanowire-based transistors or a plurality of fin-based transistors.
6 . An integrated circuit structure, comprising:
a front-side structure comprising:
a device layer having a plurality of nanowire-based or fin-based transistors; and
a plurality of metallization layers above the nanowire-based or fin-based transistors of the device layer, wherein one of the metal layers includes an array of uninterrupted signal lines comprising a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin; and
a backside structure below the nanowire-based or fin-based transistors of the device layer, the backside structure including a ground metal line.
7 . The integrated circuit structure of claim 6 , wherein the backside structure includes a stack of backside conductive structures that terminate at a conductive bump.
8 . The integrated circuit structure of claim 6 , wherein the device layer of the front-side structure further includes a trench contact, a gate contact or a contact via.
9 . The integrated circuit structure of claim 6 , wherein the front-side structure comprises a deep via layer between the nanowire-based or fin-based transistors of the device layer and the backside structure.
10 . The integrated circuit structure of claim 6 , wherein the nanowire-based or fin-based transistors device layer are memory nanowire-based or fin-based transistors.
11 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a device layer having a plurality of transistors; and
a plurality of metallization layers above the plurality of transistors of the device layer, wherein one or more of the metal layers comprises a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.
12 . The computing device of claim 11 , further comprising:
a memory coupled to the board.
13 . The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
15 . The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
16 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a front-side structure comprising:
a device layer having a plurality of nanowire-based or fin-based transistors; and
a plurality of metallization layers above the nanowire-based or fin-based transistors of the device layer, wherein one of the metal layers includes an array of uninterrupted signal lines comprising a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin; and
a backside structure below the nanowire-based or fin-based transistors of the device layer, the backside structure including a ground metal line.
17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.
18 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.
20 . The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.