IP Library › Granted Patent US 12,471,392
Granted Patent B2
US 12,471,392 · App. 18/094,131 · Granted Nov 11, 2025

Semiconductor detector and method of manufacturing same

Inventors: Kazuyuki Hozawa (Tokyo, JP); Takashi Takahama (Tokyo, JP)
Assignee: HITACHI HIGH-TECH ANALYSIS CORPORATION
H10F30/2955H10F71/121H10F77/1223H10F77/206
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Quick Facts
Patent No.
US 12,471,392
App. No.
18/094,131
Granted
Nov 11, 2025
Kind
B2
Abstract

An semiconductor detector includes an n-type semiconductor substrate, a detection electrode formed on a first surface of the semiconductor substrate, a plurality of drift electrodes formed to surround the detection electrode and applied with a voltage causing a potential gradient in which a potential changes toward the detection electrode, a radiation incidence window provided on a second surface of the semiconductor substrate, a P-type semiconductor region formed by adding boron to a surface side on the second surface of the semiconductor substrate through the radiation incidence window, and a depleting electrode causing a reverse bias between the P-type semiconductor region formed on the second surface and an N-type semiconductor region formed in the semiconductor substrate. F is added to the P-type semiconductor region, and a region with the highest concentration of F is located deeper than a region with the highest concentration of B.

Claims (16)

1 . A semiconductor detector comprising:

an n-type semiconductor substrate;

a detection electrode formed on a first surface of the n-type semiconductor substrate and configured to collect charges generated by incidence of radiation;

a plurality of drift electrodes formed surrounding the detection electrode and applied with a voltage causing a potential gradient in which a potential changes toward the detection electrode so that the charges move toward the detection electrode; and

a radiation incidence window provided on a second surface of the n-type semiconductor substrate;

a P-type semiconductor region formed by adding boron to a surface side of the second surface through the radiation incidence window; and

a depleting electrode causing a reverse bias between the P-type semiconductor region formed on the second surface and an N-type semiconductor region formed in the n-type semiconductor substrate,

wherein fluorine is additionally added to the P-type semiconductor region, and

wherein a region with the highest concentration of fluorine is positioned more closely to the surface side of the second surface than a region with the highest concentration of boron.

2 . The semiconductor detector of claim 1 , wherein the semiconductor detector comprises a first concentration-decreasing portion in which the concentration of fluorine decreases along a depth direction from the surface of the second surface and a second concentration-decreasing portion in which the concentration of fluorine decreases along the depth direction from the first concentration-decreasing portion, the second concentration-decreasing portion being located deeper than the first concentration-decreasing portion,

the second concentration-decreasing portion is configured such that the concentration of the fluorine decreases more gently than that of the first concentration-decreasing portion, and a distribution of the fluorine is located deeper than a distribution of the boron.

3 . A method of manufacturing the semiconductor detector according to claim 1 or claim 2 , the method comprising:

a P-type semiconductor region formation step in which boron is added to a surface of an n-type semiconductor substrate so that a P-type semiconductor region is formed in the n-type semiconductor substrate,

wherein the P-type semiconductor region formation step comprises a fluorine addition step in which fluorine is added to the surface of the n-type semiconductor substrate, and

the fluorine addition step comprises a fluorine implantation step of implanting fluorine and a heat treatment step of performing heat treatment after the fluorine implantation step.

4 . The method of claim 3 , wherein, in the heat treatment step, the heat treatment is performed at a temperature of 800° or below.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2025
From: HOZAWA, KAZUYUKI; TAKAHAMA, TAKASHI
To: HITACHI HIGH-TECH SCIENCE CORPORATION
Reel/Frame 071707/0187 →
CHANGE OF NAME Recorded Jul 14, 2025
From: HITACHI HIGH-TECH SCIENCE CORPORATION
To: HITACHI HIGH-TECH ANALYSIS CORPORATION
Reel/Frame 071701/0397 →
Priority Claims (1)
JP 2022-037744 · Mar 11, 2022 · national
Continuity (1)
Related Publication 20230290896A1 · Sep 14, 2023
References Cited (1)
EP 3907533A · 2021 [cited by applicant]