Granted Patent B2

US 12,474,404 · App. 18/268,517 · Granted Nov 18, 2025

Inventors: Mo Chen (Guangdong, CN); Zhijun Fan (Guangdong, CN); Jianbo Liu (Guangdong, CN); Chao Xu (Guangdong, CN)

Assignee: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.

G01R31/31727G11C29/12015

Abstract

Claims (39)

1 . A test circuit, comprising:

a clock driving circuit, configured to provide clock signals with different configurations to a to-be-tested sequential circuit, wherein the clock driving circuit comprises a first clock driving circuit, and the first clock driving circuit comprises:

a plurality of first clock paths, configured to provide corresponding clock signals, respectively; and

a logic gate circuit, configured to generate a first clock signal with an adjusted pulse width for the to-be-tested sequential device based on at least part of clock signals provided by the plurality of first clock paths; and

a verification circuit, configured to verify an output of the to-be-tested sequential circuit under the clock signal with each configuration.

2 . The test circuit according to claim 1 , wherein the verification circuit comprises:

a reference sequential circuit, wherein a test sequence is synchronously provided to the reference sequential circuit and the to-be-tested sequential circuit, and the first clock driving circuit further provides a second clock signal to the reference sequential circuit; and

a comparison module, configured to compare an output of the reference sequential circuit with the output of the to-be-tested sequential circuit.

3 . The test circuit according to claim 1 , wherein the plurality of first clock paths receive a common clock input and provide clock signals with different phases based on the clock input, respectively.

4 . The test circuit according to claim 1 , wherein at least one of the first clock paths further comprises:

a first selector, configured to select a clock signal from clock signals provided by a plurality of sub-paths of the corresponding first clock path and provide the selected clock signal to the logic gate circuit.

5 . The test circuit according to claim 1 , wherein the clock driving module further comprises a second clock driving circuit, and wherein the second clock driving circuit comprises:

a plurality of second clock paths, configured to provide clock signals with different phases, respectively, wherein at least one of the plurality of second clock paths provides a clock signal based on the first clock signal; and

a second selector, configured to select a clock signal from the clock signals provided by the plurality of second clock paths for the to-be-tested sequential device.

6 . The test circuit according to claim 1 , wherein the clock driving circuit further comprises a third clock driving circuit, and wherein the third clock driving circuit comprises:

a plurality of third clock paths, configured to provide clock signals with different phases, respectively; and

a third selector, configured to select a clock signal from the clock signals provided by the plurality of third clock paths for at least one of the plurality of first clock paths.

7 . The test circuit according to claim 6 , wherein the plurality of first clock paths comprise at least a first path and a second path;

the first path provides the selected clock signal to the logic gate circuit; and

the second path provides an inverted version or an inverted and delayed version of the selected clock signal to the logic gate circuit.

8 . The test circuit according to claim 7 , wherein the second path comprises:

an inverter, configured to receive the selected clock signal and generate a clock signal which is inverted to the selected clock signal;

one or more sub-paths, configured to provide corresponding versions of the inverted clock signal to a fourth selector, respectively; and

the fourth selector, configured to select a version from the different versions of the inverted clock signal and provide the selected version to the logic gate circuit.

9 . The test circuit according to claim 8 , wherein the one or more sub-paths provide different delayed versions of the inverted clock signal to the fourth selector, respectively.

10 . The test circuit according to claim 1 , wherein the logic gate circuit is an AND gate or an OR gate.

11 . The test circuit according to claim 1 , further comprising a check module configured to check the output of the to-be-tested sequential circuit by using a check code in a test sequence provided to the to-be-tested sequential device.

12 . The test circuit according to claim 1 , wherein the sequential circuit is a flip-flop or a latch.

13 . The test circuit according to claim 1 , further comprising an additional sequential circuit associated with the to-be-tested sequential circuit.

14 . A computing system, comprising the test circuit according to claim 1 .

15 . A test method for a test circuit for testing sequential circuit in pipeline stage, wherein the test circuit is the test circuit according to claim 1 , and

the method comprises:

providing clock signals with different configurations to the to-be-tested sequential circuit by the clock driving circuit;

providing a test sequence to an input of the to-be-tested sequential circuit; and

detecting whether an output of the to-be-tested sequential circuit meets a requirement under the clock signal with each configuration.

16 . The method according to claim 15 , further comprising:

determining a corresponding clock configuration or clock configuration range that meets the requirement;

determining a difference between a predetermined timing parameter range designed for the to-be-tested sequential circuit and the corresponding clock configuration determined to meet the requirement through testing; and

modifying, a circuit design of the to-be-tested sequential circuit and/or process parameters for manufacturing the to-be-tested sequential circuit according to the difference.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (45)