IP Library › Granted Patent US 12,474,941
Granted Patent B2
US 12,474,941 · App. 17/561,913 · Granted Nov 18, 2025

Kernel source adaptation for execution on a graphics processing unit

Inventors: Hisham Chowdhury (El Dorado Hills, CA); Guei-Yuan Lueh (San Jose, CA); Kai Chen (Folsom, CA)
Assignee: Intel Corporation
G06F9/4552G06T1/20G06F9/4401
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Quick Facts
Patent No.
US 12,474,941
App. No.
17/561,913
Granted
Nov 18, 2025
Kind
B2
Abstract

Examples described herein relate to computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: access a kernel source written in a shading language; select a compiler from a plurality of compilers based on the shading language; generate a kernel instruction set architecture and an associated runtime binding based on the kernel source and the selected compiler; and adapt state information to configure a graphics processing unit (GPU) based on the runtime binding to target any API runtime of choice.

Claims (44)

1 . At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:

execute a user mode driver that is to:

access a kernel source written in a shading language;

select a compiler from a plurality of compilers based on the shading language;

generate a kernel instruction set architecture and an associated runtime binding based on the kernel source and the selected compiler; and

adapt state information to configure a graphics processing unit (GPU) based on the runtime binding, wherein the runtime binding indicates: registers for passing values for arguments to particular GPU assembly language level instructions, a number of threads to dispatch, and state programming to execute the GPU assembly language level instructions.

2 . The computer-readable medium of claim 1 , wherein the shading language comprises one or more of: C for Metal (CM), High-level shader language (HLSL), OpenCL, Standard Portable Intermediate Representation V (SPIR-V), Metal Shading Language (Metal SL), or CUDA.

3 . The computer-readable medium of claim 1 , wherein the plurality of compilers comprise one or more of: DirectX Bytecode (DXBC) compiler, where DXBC can be an intermediate representation of DirectX-based High-Level Shading Language (HLSL); vector compiler; OpenCL compiler, SpirV compiler, Metal Shading Language (Metal SL) compiler, or CUDA compiler.

4 . The computer-readable medium of claim 1 , wherein the compiler is selected based on the shading language.

5 . The computer-readable medium of claim 1 , wherein the kernel instruction set architecture generated by the compiler is unchanged by adaptation of state information to configure the GPU.

6 . The computer-readable medium of claim 1 , wherein the state information comprises one or more of: resource binding mode, resource type information, single instruction multiple data (SIMD) mode, number of threads to dispatch and how to break a thread size, and/or variables.

7 . The computer-readable medium of claim 1 , wherein the generate a kernel instruction set architecture and an associated runtime binding is based on a just in time (JIT) operation using the selected compiler.

8 . The computer-readable medium of claim 1 , wherein the adapt state information to configure a GPU based on the runtime binding occurs using a user mode driver (UMD) at workload execution.

9 . The computer-readable medium of claim 1 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:

deploy the generated kernel instruction set architecture for execution on the GPU configured using the adapted state information.

10 . An apparatus comprising:

a processor and

a machine-readable storage storing instructions, the instructions executable by the processor to cause the processor to:

access a kernel source written in a shading language;

select a compiler from a plurality of compilers based on the shading language;

generate a kernel instruction set architecture and an associated runtime binding based on the kernel source and the selected compiler; and

adapt state information to configure a graphics processing unit (GPU) based on the runtime binding, wherein the runtime binding indicates: registers for passing values for arguments to particular GPU assembly language level instructions, a number of threads to dispatch, and state programming to execute the GPU assembly language level instructions.

11 . The apparatus of claim 10 , wherein the shading language comprises one or more of: C for Metal (CM), High-level shader language (HLSL), OpenCL, Standard Portable Intermediate Representation V (SPIR-V), Metal Shading Language (Metal SL), or CUDA.

12 . The apparatus of claim 10 , wherein the plurality of compilers comprise one or more of: DirectX Bytecode (DXBC) compiler, where DXBC can be an intermediate representation of DirectX-based High-Level Shading Language (HLSL); vector compiler; OpenCL compiler, SpirV compiler, Metal Shading Language (Metal SL) compiler, or CUDA compiler.

13 . The apparatus of claim 10 , wherein the compiler is selected based on the shading language.

14 . The apparatus of claim 10 , wherein the kernel instruction set architecture generated by the compiler is unchanged by adaptation of state information to configure the GPU.

15 . The apparatus of claim 10 , wherein the state information comprises resource binding mode, resource type information, single instruction multiple data (SIMD) mode, number of threads to dispatch and how to break a thread size, and/or variables.

16 . The apparatus of claim 10 , wherein the generate a kernel instruction set architecture and an associated runtime binding is based on a just in time (JIT) operation using the selected compiler.

17 . The apparatus of claim 10 , wherein the processor is to execute a user mode driver (UMD) to adapt state information to configure a GPU based on the runtime binding.

18 . The apparatus of claim 10 , further comprising the GPU to perform the generated kernel instruction set architecture using the adapted state information.

19 . A method comprising:

accessing a kernel source written in a shading language;

selecting a compiler from a plurality of compilers based on the shading language;

generating a kernel instruction set architecture and an associated runtime binding based on the kernel source and the selected compiler; and

adapting state information to configure a graphics processing unit (GPU) based on the runtime binding, wherein the runtime binding indicates: registers for passing values for arguments to particular GPU assembly language level instructions, a number of threads to dispatch, and state programming to execute the GPU assembly language level instructions.

20 . The method of claim 19 , wherein

the shading language comprises one or more of: C for Metal (CM), High-level shader language (HLSL), OpenCL, Standard Portable Intermediate Representation V (SPIR-V), Metal Shading Language (Metal SL), or CUDA and

the plurality of compilers comprise one or more of: DirectX Bytecode (DXBC) compiler, where DXBC can be an intermediate representation of DirectX-based High-Level Shading Language (HLSL); vector compiler; OpenCL compiler, SpirV compiler, Metal Shading Language (Metal SL) compiler, or CUDA compiler.

21 . The method of claim 19 , wherein the compiler is selected based on the shading language.

22 . The method of claim 19 , wherein the kernel instruction set architecture generated by the compiler is unchanged by adaptation of state information to configure the GPU.

23 . The method of claim 19 , wherein the state information comprises: resource binding mode, resource type information, single instruction multiple data (SIMD) mode, number of threads to dispatch and how to break a thread size, and/or variables.

24 . The method of claim 19 , wherein the generating a kernel instruction set architecture and an associated runtime binding is based on a just in time (JIT) operation using the selected compiler.

25 . The method of claim 19 , comprising:

deploying the generated kernel instruction set architecture for execution on the GPU configured using the adapted state information.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2022
From: CHOWDHURY, HISHAM; LUEH, GUEI-YUAN; CHEN, KAI
To: INTEL CORPORATION
Reel/Frame 058879/0177 →
Continuity (1)
Related Publication 20230205559A1 · Jun 29, 2023
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