Semiconductor package structure

1 . A semiconductor package structure, comprising:

a substrate comprising a silicon layer;

a first electronic component disposed over the substrate; and

an electronic device at least partially embedded in the silicon layer and comprising:

a second electronic component configured for providing a regulated voltage to the first electronic component; and

a reinforcement supporting the second electronic component,

wherein the silicon layer has a through hole penetrating the silicon layer from a top surface to a bottom surface of the silicon layer, and the electronic device is in the through hole of the silicon layer.

2 . The semiconductor package structure as claimed in claim 1 , wherein the substrate further comprises a through silicon via (TSV) penetrating the silicon layer from the top surface to the bottom surface of the silicon layer and disposed at a lateral side of the electronic device.

3 . The semiconductor package structure as claimed in claim 1 , wherein the reinforcement comprises;

a first encapsulant covering a first side of the electronic device and free from extending between the second electronic component and the silicon layer; and

a second encapsulant covering a second side of the electronic device and free from extending between the second electronic component and the silicon layer, the second side being opposite to the first side.

4 . The semiconductor package structure as claimed in claim 3 , wherein the electronic device further comprises a first conductive pillar encapsulated by the first encapsulant and a second conductive pillar encapsulated by the second encapsulant, and the first encapsulant is spaced apart from the second encapsulant by the electronic device.

5 . The semiconductor package structure as claimed in claim 3 , wherein the electronic device further comprises a first conductive pillar penetrating the first encapsulant and electrically connecting the second electronic component to the first electronic component, and a top surface of the first conductive pillar substantially aligns with the top surface of the silicon layer.

6 . The semiconductor package structure as claimed in claim 1 , further comprising a through silicon via (TSV) penetrating the silicon layer from the top surface to the bottom surface of the silicon layer and electrically connected to the first electronic component.

7 . The semiconductor package structure as claimed in claim 6 , further comprising a conductive via over the electrically connected to the TSV, wherein a width of the conductive via is less than a width of the TSV.

8 . The semiconductor package structure as claimed in claim 1 , further comprising a heat dissipating via extending along an inner sidewall of the through hole, wherein a height of the heat dissipating via is substantially the same as a depth of the through hole.

9 . The semiconductor package structure as claimed in claim 8 , further comprising an insulating layer surrounding the heat dissipating via and contacting the inner sidewall of the through hole.

10 . The semiconductor package structure as claimed in claim 1 , further comprising an insulation layer contacting the bottom surface of the silicon layer and exposed to the through hole.

11 . The semiconductor package structure as claimed in claim 10 , further comprising:

a conductive pad within the insulation layer; and

a conductive pillar encapsulated by the reinforcement and electrically connecting the conductive pad to the second electronic component.

12 . The semiconductor package structure as claimed in claim 1 , further comprising a first conductive pillar in the through hole and connected to a top surface of the electronic device.

13 . The semiconductor package structure as claimed in claim 12 , further comprising a redistribution layer (RDL) on the top surface of the silicon layer and electrically connecting the first conductive pillar to the first electronic component.

14 . The semiconductor package structure as claimed in claim 1 , wherein the electronic device further comprises a third electronic component stacked on the second electronic component, and the reinforcement comprises an encapsulant structure encapsulating the second electronic component and the third electronic component.

15 . The semiconductor package structure as claimed in claim 14 , wherein the reinforcement comprises a first encapsulant encapsulating a top surface of the third electronic component and a second encapsulant encapsulating a bottom surface of the second electronic component.

16 . The semiconductor package structure as claimed in claim 14 , further comprising an adhesion layer between and electrically isolating the second electronic component and the third electronic component.

17 . The semiconductor package structure as claimed in claim 14 , further comprising a conductive structure in the through hole and surrounding the second electronic component and the third electronic component.

18 . The semiconductor package structure as claimed in claim 17 , wherein the substrate further comprises a plurality of conductive vias penetrating the silicon layer from the top surface to the bottom surface of the silicon layer, and a top surface of the conductive structure substantially aligns with top surfaces of the conductive vias.

19 . The semiconductor package structure as claimed in claim 18 , wherein a bottom surface of the conductive structure substantially aligns with bottom surfaces of the conductive vias.

20 . The semiconductor package structure as claimed in claim 17 , further comprising a bonding layer connecting the second electronic component to the third electronic component, wherein the conductive structure surrounds the bonding layer.