IP Library › Granted Patent US 12,477,794
Granted Patent B2
US 12,477,794 · App. 17/711,707 · Granted Nov 18, 2025

Semiconductor device and manufacturing method thereof

Inventors: Yan-Ting Lin (Hsinchu County, TW); Chien-I Kuo (Chiayi County, TW); Chii-Horng Li (Hsinchu County, TW); Yee-Chia Yeo (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10D62/151H10D30/031H10D30/6735H10D30/6757H10D30/797H01L21/02433H01L21/02532H01L21/02609H01L21/0262H10D62/116H10D62/118H10D62/405H10D62/834H10D64/017H10D64/018H10D64/20
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Quick Facts
Patent No.
US 12,477,794
App. No.
17/711,707
Granted
Nov 18, 2025
Kind
B2
Abstract

A method includes forming a plurality of channel layers above a (110)-orientated substrate, the channel layers arranged in a <110> direction normal to a top surface the (110)-orientated substrate and extending in a <1 1 0> direction perpendicular to the <110> direction; epitaxial growing a plurality of silicon layers on either side of each of the channel layers; doping the silicon layers with boron; epitaxial growing a plurality of first silicon germanium layers on the silicon layers; forming a gate structure surrounding each of the channel layers.

Claims (38)

1 . A method, comprising:

forming a plurality of channel layers above a (110)-orientated substrate, the channel layers arranged in a <110> direction normal to a top surface of the (110)-orientated substrate and extending in a <110> direction perpendicular to the <110> direction;

epitaxial growing a plurality of silicon layers on either side of each of the channel layers;

doping the silicon layers with boron;

epitaxial growing a plurality of first silicon germanium layers on the silicon layers;

forming a gate structure surrounding each of the channel layers; and

epitaxial growing a plurality of second silicon germanium layers on the first silicon germanium layers, the second silicon germanium layers having a higher germanium atomic concentration than the first silicon germanium layers.

2 . The method of claim 1 , wherein after epitaxial growing the silicon layers, the silicon layers each has a rectangular profile from a cross sectional view.

3 . The method of claim 1 , wherein after epitaxial growing the silicon layers, a top surface of one of the silicon layers is in parallel with a bottom surface of a next one of the silicon layers above the one of the silicon layers.

4 . The method of claim 1 , wherein epitaxial growing the silicon layers exhibits a facet growth behavior on a (111)-orientation.

5 . The method of claim 1 , wherein epitaxial growing the silicon layers is performing by introducing a mixture gas comprising SiH4 and B2H6 on the (110)-orientated substrate.

6 . The method of claim 1 , further comprising:

doping the first silicon germanium layers with the boron, the silicon layers having a higher boron concentration than the first silicon germanium layers after doping the first silicon germanium layers.

7 . The method of claim 1 , wherein the silicon layers each has a germanium atomic concentration less than the first silicon germanium layers.

8 . The method of claim 1 , wherein the silicon layers each has a germanium atomic concentration less than about 10 at. %.

9 . The method of claim 1 , wherein the silicon layers are free from germanium.

10 . A method, comprising:

forming a multi-layer stack including alternating a plurality of channel layers and a plurality of sacrificial layers stacked in a vertical direction on a silicon substrate having a (110) surface orientation;

forming a plurality of inner spacers on either side of each of the sacrificial layers;

forming a plurality of epitaxial buffer layers on either side of each of the channel layers, wherein one of the epitaxial buffer layers has a notched corner, and a corresponding one of the inner spacers is inlaid in the notched corner;

doping the epitaxial buffer layers with a dopant;

forming a plurality of epitaxial source/drain regions on the epitaxial buffer layers, wherein each of the epitaxial source/drain regions is on three sides of a corresponding one of the epitaxial buffer layers and is made of a different material than the epitaxial buffer layers; and

replacing the sacrificial layers with a gate structure.

11 . The method of claim 10 , wherein the channel layers each has a length extending along a <110> direction on the (110) surface orientation.

12 . The method of claim 10 , wherein the epitaxial buffer layers are made of silicon, and the epitaxial source/drain regions are made of silicon germanium.

13 . The method of claim 10 , wherein the dopant comprises boron.

14 . The method of claim 10 , wherein the gate structure is of a p-type metal-oxide-semiconductor device.

15 . The method of claim 10 , wherein end surfaces of the channel layers share a border with the inner spacers.

16 . The method of claim 10 , wherein end surfaces of the channel layers are concave.

17 . A method for forming a semiconductor device, comprising:

forming a plurality of channel layers above a (110)-orientated substrate, the channel layers extending in a <110> direction on the (110)-orientated substrate and arranged in a vertical direction, wherein end surfaces of the channel layers are concave;

forming a gate structure surrounding each of the channel layers;

forming a plurality of source/drain structures on either side of the gate structure;

forming a plurality of inner spacers interposing the gate structure and the source/drain structures; and

forming a plurality of silicon buffer layers interposing the channel layers and the source/drain structures, the silicon buffer layers each having two horizontal side surfaces and a vertical side surface between the two horizontal side surfaces from a cross sectional view.

18 . The method of claim 17 , wherein one of the silicon buffer layers has a notched corner, and a corresponding one of the inner spacers is inlaid in the notched corner.

19 . The method of claim 17 , wherein end surfaces of the channel layers share a border with the inner spacers.

20 . The method of claim 17 , wherein the plurality of silicon buffer layers include germanium.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2022
From: LIN, YAN-TING; KUO, CHIEN-I; LI, CHII-HORNG; YEO, YEE-CHIA
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 059642/0991 →
Continuity (1)
Related Publication 20230317791A1 · Oct 5, 2023
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