IP Library › Granted Patent US 12,477,826
Granted Patent B2
US 12,477,826 · App. 17/860,593 · Granted Nov 18, 2025

Display device and method of fabricating the same

Inventors: Hyung Jun Kim (Seoul, KR); So Young Koo (Hwaseong-si, KR); Eok Su Kim (Seoul, KR); Yun Yong Nam (Hwaseong-si, KR); Jun Hyung Lim (Seoul, KR); Kyung Jin Jeon (Incheon, KR)
Assignee: Samsung Display Co., Ltd.
H10D86/60H01L25/167H10D86/0231H10D86/451H01L24/24H01L24/25H01L2224/24051H01L2224/24147H01L2224/25175H01L2924/12041H10H20/857
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Quick Facts
Patent No.
US 12,477,826
App. No.
17/860,593
Granted
Nov 18, 2025
Kind
B2
Abstract

A display device includes a first conductive layer including a first voltage line and a second voltage line, a buffer layer, a semiconductor layer including a first active layer and a second active layer, a first gate insulating layer, a second conductive layer including a first gate electrode overlapping the first active layer and a second gate electrode overlapping the second active layer, a passivation layer, a via layer, a bank pattern layer including a first bank pattern and a second bank pattern partially spaced apart from each other, a third conductive layer including a first electrode and a second electrode spaced apart from each other, and light emitting elements. The passivation layer includes silicon nitride (SiN x ), and a ratio of a number of silicon-hydrogen bonds (Si—H) to a number of nitrogen-hydrogen bonds (N—H) in the silicon nitride (SiN x ) is in a range of about 1:0.6 to about 1:1.5.

Claims (82)

1 . A display device comprising:

a first conductive layer disposed on a substrate and comprising a first voltage line and a second voltage line;

a buffer layer disposed on the first conductive layer;

a semiconductor layer comprising a first active layer and a second active layer disposed on the buffer layer;

a first gate insulating layer disposed on the semiconductor layer;

a second conductive layer disposed on the first gate insulating layer and comprising:

a first gate electrode overlapping the first active layer in a plan view; and

a second gate electrode overlapping the second active layer in a plan view;

a passivation layer disposed on the second conductive layer and the semiconductor layer;

a via layer disposed on the passivation layer;

a bank pattern layer disposed on the via layer and comprising a first bank pattern and a second bank pattern partially spaced apart from each other;

a third conductive layer disposed on the bank pattern layer and comprising a first electrode and a second electrode spaced apart from each other; and

light emitting elements disposed on the first electrode and the second electrode of the third conductive layer, wherein

the passivation layer comprises silicon nitride (SiN x ),

a ratio of a number of silicon-hydrogen bonds (Si—H) to a number of nitrogen-hydrogen bonds (N—H) in the silicon nitride (SiN x ) is in a range of about 1:0.6 to about 1:1.5,

a first electrode contact hole that penetrates the bank pattern layer, the via layer, and the passivation layer; and

a second electrode contact hole that penetrates the bank pattern layer, the via layer, the passivation layer, and the buffer layer.

2 . The display device of claim 1 , wherein a diameter of each of the first electrode contact hole and the second electrode contact hole measured on an upper surface of the bank pattern layer is in a range of about 4 to about 10 μm.

3 . The display device of claim 1 , wherein

the first electrode contact hole exposes a part of the first active layer,

the second electrode contact hole exposes a part of the second voltage line,

the first electrode directly contacts the first active layer through the first electrode contact hole, and

the second electrode directly contacts the second voltage line through the second electrode contact hole.

4 . The display device of claim 1 , wherein

the light emitting elements are disposed between the first bank pattern and the second bank pattern,

the first electrode is disposed on the first bank pattern, and

the second electrode is disposed on the second bank pattern.

5 . The display device of claim 1 , further comprising:

a first insulating layer that is disposed on the third conductive layer,

wherein the light emitting elements are disposed directly on the first insulating layer.

6 . The display device of claim 5 , comprising:

a second insulating layer disposed on the light emitting elements;

a third insulating layer disposed on the second insulating layer;

a first connection electrode disposed on the first electrode and electrically contacting first ends of the light emitting elements; and

a second connection electrode disposed on the second electrode and electrically contacting second ends of the light emitting elements.

7 . The display device of claim 5 , further comprising:

a bank layer that is disposed on the first insulating layer and surrounds an area where the light emitting elements are disposed.

8 . A display device comprising

a first conductive layer disposed on a substrate and comprising a first voltage line and a second voltage line;

a buffer layer disposed on the first conductive layer;

a semiconductor layer comprising a first active layer and a second active layer disposed on the buffer layer;

a first gate insulating layer disposed on the semiconductor layer;

a second conductive layer disposed on the first gate insulating layer and comprising:

a first gate electrode overlapping the first active layer in a plan view; and

a second gate electrode overlapping the second active layer in a plan view;

a passivation layer disposed on the second conductive layer and the semiconductor layer;

a via layer disposed on the passivation layer;

a bank pattern layer disposed on the via layer and comprising a first bank pattern and a second bank pattern partially spaced apart from each other;

a third conductive layer disposed on the bank pattern layer and comprising a first electrode and a second electrode spaced apart from each other; and

light emitting elements disposed on the first electrode and the second electrode of the third conductive layer, wherein

the passivation layer comprises silicon nitride (SiN x ),

a ratio of a number of silicon-hydrogen bonds (Si—H) to a number of nitrogen-hydrogen bonds (N—H) in the silicon nitride (SiN x ) is in a range of about 1:0.6 to about 1:1.5, and

the passivation layer directly contacts the first active layer and the second active layer.

9 . A display device comprising

a first conductive layer disposed on a substrate and comprising a first voltage line and a second voltage line;

a buffer layer disposed on the first conductive layer;

a semiconductor layer comprising a first active layer and a second active layer disposed on the buffer layer;

a first gate insulating layer disposed on the semiconductor layer;

a second conductive layer disposed on the first gate insulating layer and comprising:

a first gate electrode overlapping the first active layer in a plan view; and

a second gate electrode overlapping the second active layer in a plan view;

a passivation layer disposed on the second conductive layer and the semiconductor layer;

a via layer disposed on the passivation layer;

a bank pattern layer disposed on the via layer and comprising a first bank pattern and a second bank pattern partially spaced apart from each other;

a third conductive layer disposed on the bank pattern layer and comprising a first electrode and a second electrode spaced apart from each other; and

light emitting elements disposed on the first electrode and the second electrode of the third conductive layer, wherein

the passivation layer comprises silicon nitride (SiN x ),

a ratio of a number of silicon-hydrogen bonds (Si—H) to a number of nitrogen-hydrogen bonds (N—H) in the silicon nitride (SiN x ) is in a range of about 1:0.6 to about 1:1.5,

the first conductive layer further comprises:

a bottom metal layer overlapping the first active layer in a plan view; and

a data line electrically connected to the second active layer, and

the third conductive layer further comprises a plurality of electrode patterns electrically connected to any one of the first voltage line, the data line, and the first gate electrode.

10 . The display device of claim 9 , wherein the first electrode directly contacts the bottom metal layer through a third electrode contact hole penetrating the bank pattern layer, the via layer, the passivation layer, and the buffer layer.

11 . The display device of claim 9 , wherein

the electrode patterns comprise a first electrode pattern, and

the first electrode pattern directly contacts the first gate electrode through a first contact hole penetrating the bank pattern layer, the via layer, and the passivation layer and directly contacts the second active layer through a second contact hole penetrating the bank pattern layer, the via layer, and the passivation layer.

12 . The display device of claim 9 , wherein

the electrode patterns comprise a second electrode pattern, and

the second electrode pattern directly contacts the second active layer through a third contact hole penetrating the bank pattern layer, the via layer, and the passivation layer and directly contacts the data line through a fourth contact hole penetrating the bank pattern layer, the via layer, the passivation layer, and the buffer layer.

13 . The display device of claim 9 , wherein

the electrode patterns comprise a third electrode pattern, and

the third electrode pattern directly contacts the first active layer through a fifth contact hole penetrating the bank pattern layer, the via layer, and the passivation layer and directly contacts the first voltage line through a sixth contact hole penetrating the bank pattern layer, the via layer, the passivation layer, and the buffer layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2022
From: KIM, HYUNG JUN; KOO, SO YOUNG; KIM, EOK SU; NAM, YUN YONG; LIM, JUN HYUNG; JEON, KYUNG JIN
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 060617/0876 →
Priority Claims (1)
KR 10-2021-0141694 · Oct 22, 2021 · national
Continuity (1)
Related Publication 20230127261A1 · Apr 27, 2023
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