Systems and methods for using internal memory of a system on chip in a security boot
A computing system is provided. The computing system includes a system on a chip. The system on a chip includes a processor and an internal memory. The computing system further includes a root of trust hardware connected to the internal memory and configured to intercept commands from the processor to the internal memory.
1 . A computing system comprising:
a system on a chip including a processor, an internal memory, and a selector, the system on a chip further including a plurality of ports that includes a first port and a second port, the selector being configured to connect the internal memory to the processor, via the first port, in a first configuration in which the processor has direct access to the internal memory, the selector being further configured to connect the internal memory to the processor, via the second port, in a second configuration in which the process has indirect access to the internal memory;
a root of trust (RoT) hardware connected to the internal memory and configured to intercept commands from the processor to the internal memory, the RoT hardware being positioned outside the system on a chip and coupled to both the first port and the second port, the first port providing access to intercept commands from the processor before the commands are received by the internal memory or by the selector, the second port providing access to the internal memory, via the selector, to filter all commands from the processor to the internal memory via the RoT hardware in the second configuration.
2 . The system of claim 1 , wherein the selector includes a fuse.
3 . The system of claim 1 , wherein the system on a chip is a baseband management controller (BMC).
4 . The system of claim 1 , wherein the internal memory is a flash memory.
5 . The system of claim 1 , wherein the processor communicates with the internal memory via a serial peripheral interface (SPI).
6 . The system of claim 5 , wherein the SPI connects first with the ROT hardware.
7 . The system of claim 5 , wherein the ROT hardware is further configured to pass an expected command of the commands directly to the internal memory.
8 . The system of claim 5 , wherein the ROT hardware is further configured to prevent an unexpected command of the commands from passing to the internal memory.
9 . A method, comprising:
connecting a root of trust (RoT) hardware to ports on a system on a chip, the system on a chip including a processor, an internal memory, and a selector, the ports including a plurality of ports that includes a first port and a second port, the RoT hardware being positioned outside the system on a chip and being coupled to both the first port and the second port;
setting the selector in a first configuration, wherein in the first configuration communications are routed from the processor, via the selector, directly to the internal memory, the first configuration being achieved via the first port that couples the processor to the internal memory directly through the selector; and
setting the selector in a second configuration, wherein in the second configuration communications are routed from the processor through the ROT hardware indirectly, via the selector, the second configuration being achieved via the second port that couples the processor to the internal memory indirectly through the ROT hardware and the selector.
10 . The method according to claim 9 , wherein the ports on the system on a chip are serial peripheral interface (SPI) ports.
11 . The method according to claim 10 , wherein the ROT root of trust hardware is configured to pass an expected command of the commands directly to the internal memory.
12 . The method according to claim 10 , wherein the ROT root of trust hardware is configured to prevent an unexpected command of the commands from passing to the internal memory.
13 . The method according to claim 9 , wherein setting the selector in the first configuration includes disconnecting a fuse using a one-time programmable register.
14 . The method according to claim 9 , wherein the system on a chip is a baseband management controller (BMC).
15 . The method according to claim 9 , wherein the internal memory is a flash memory.
16 . The method according to claim 15 , wherein the flash memory includes a firmware image.