Granted Patent B2

US 12,482,388 · App. 17/771,913 · Granted Nov 25, 2025

Inventor: Zhixiang Chen (Guangdong, CN)

Assignee: TCL China Star Optoelectronics Technology Co., Ltd.

G09G3/20G09G2300/0408G09G2310/0267G09G2330/02

Abstract

Claims (73)

1 . A gate driving circuit, comprising a plurality of cascaded gate driving units, each of the gate driving unit comprising:

a pull-up control module;

a pull-up module, electrically connected to the pull-up control module through a first node and electrically connected to a scan line;

a pull-down module, electrically connected to the scan line;

a first pull-down maintaining module, comprising:

a first pull-down maintaining transistor, having a drain connected to the first node; and

a first auxiliary module, electrically connected to a gate of the first pull-down maintaining transistor, configured to control an on/off state of the first pull-down maintaining transistor; and

a second pull-down maintaining module, comprising:

a second pull-down maintaining transistor, having a gate electrically connected to a second pull-down maintaining line to receive a second pull-down maintaining signal, a source electrically connected to the first pull-down maintaining transistor and a first power line to receive a first power signal, and a drain electrically connected to the first node;

wherein the first auxiliary module comprises:

a first auxiliary transistor, having a drain electrically connected to the gate of the first pull-down maintaining transistor, a source electrically connected to an auxiliary power line to receive an auxiliary signal, and a gate connected to a first control signal line to receive a first control signal;

wherein the first control signal is configured to turn on the first auxiliary transistor to allow the auxiliary signal to turn off the first pull-down maintaining transistor in on-state, wherein the first control signal is identical to the second pull-down maintaining signal, and the second pull-down maintaining signal comprises alternatively-arranged high voltage levels and low voltage levels;

wherein the first pull-down maintaining transistor and the second pull-down maintaining transistor are alternatively turned on, and the first pull-down maintaining transistor and the second pull-down maintaining transistor are alternatively turned off;

wherein the first pull-down maintaining module further comprises:

a first converting module, electrically connected to the first node and the gate of the first pull-down maintaining transistor, configured to turn on the first pull-down maintaining transistor.

2 . The gate driving circuit of claim 1 , wherein the second pull-down maintaining signal is configured to turn on the second pull-down maintaining transistor to allow the first power signal to control a voltage level of the first node.

3 . The gate driving circuit of claim 2 , wherein the auxiliary power line and the first power line are a same line.

4 . The gate driving circuit of claim 2 , wherein the auxiliary power line and the first power line are different lines such that the auxiliary signal is different from the first power signal.

5 . The gate driving circuit of claim 2 , wherein the second pull-down maintaining module further comprises:

a second auxiliary module, electrically connected to a gate of the second pull-down maintaining transistor, configured to control an on/off state of the second pull-down maintaining transistor.

6 . The gate driving circuit of claim 5 , wherein the second auxiliary module further comprises:

a second auxiliary transistor, having a drain electrically connected to the gate of the second pull-down maintaining transistor, a source electrically connected to the auxiliary power line to receive the auxiliary signal, and a gate connected to a second control signal line to receive a second control signal;

wherein a gate of the first pull-down maintaining transistor is electrically connected to a first pull-down maintaining line to receive a first pull-down maintaining signal;

wherein the first pull-down maintaining signal is configured to turn on the first pull-down maintaining transistor to allow the first power signal to control the voltage level of the first node, the first pull-down maintaining signal comprises alternatively-arranged high voltage levels and low voltage levels, and the high voltage levels of the first pull-down maintaining signal are corresponding to the low voltage levels of the second pull-down maintaining signal; and

wherein the second control signal is identical to the first pull-down maintaining signal.

7 . The gate driving circuit of claim 1 , wherein the first converting module comprises a first inverter transistor, a second inverter transistor, a third inverter transistor, and a fourth inverter transistor;

a source of the first inverter transistor, a gate of the first inverter transistor, and a source of the third inverter transistor are configured to receive a first pull-down maintaining signal, and a drain of the first inverter transistor is electrically connected to a gate of the third inverter transistor; and

a gate of the second inverter transistor and a gate of the fourth inverter transistor are electrically connected to the first node, a drain of the second inverter transistor and a drain of the fourth transistor are configured to receive the first power signal, a source of the second inverter transistor is electrically connected to the drain of the first inverter transistor, and a source of the fourth inverter transistor is electrically connected to a drain of the third inverter transistor;

wherein the first pull-down maintaining signal comprises alternatively-arranged high voltage levels and low voltage levels, and the high voltage levels of the first pull-down maintaining signal are corresponding to the low voltage levels of the second pull-down maintaining signal.

8 . A gate driving circuit, comprising a plurality of cascaded gate driving units, each of the gate driving unit comprising:

a pull-up control module;

a pull-up module, electrically connected to the pull-up control module through a first node and electrically connected to a scan line;

a pull-down module, electrically connected to the scan line;

a first pull-down maintaining module, comprising:

a first pull-down maintaining transistor, having a drain connected to the first node; and

a first auxiliary module, electrically connected to a gate of the first pull-down maintaining transistor, configured to turn off the first pull-down maintaining transistor in on-state; and

a second pull-down maintaining module, comprising:

a second pull-down maintaining transistor, having a gate electrically connected to a second pull-down maintaining line to receive a second pull-down maintaining signal, a source electrically connected to the first pull-down maintaining transistor and a first power line to receive a first power signal, and a drain electrically connected to the first node; and

a second auxiliary module, electrically connected to the gate of the second pull-down maintaining transistor, configured to control an on/off state of the second pull-down maintaining transistor;

wherein the first pull-down maintaining transistor and the second pull-down maintaining transistor are alternatively turned on, and the first pull-down maintaining transistor and the second pull-down maintaining transistor are alternatively turned off;

wherein the first pull-down maintaining module further comprises:

a first converting module, electrically connected to the first node and the gate of the first pull-down maintaining transistor, configured to turn on the first pull-down maintaining transistor.

9 . The gate driving circuit of claim 8 , wherein the first auxiliary module comprises:

a first auxiliary transistor, having a drain electrically connected to the gate of the first pull-down maintaining transistor, a source electrically connected to an auxiliary power line to receive an auxiliary signal, and a gate connected to a first control signal line to receive a first control signal;

wherein the first control signal is configured to turn on the first auxiliary transistor to allow the auxiliary signal to control the on/off state of the first pull-down maintaining transistor.

10 . The gate driving circuit of claim 9 , wherein the second pull-down maintaining signal comprises alternatively-arranged high voltage levels and low voltage levels, the second pull-down maintaining signal is configured to turn on the second pull-down maintaining transistor to allow the first power signal to control a voltage level of the first node, and the first control signal is identical to the second pull-down maintaining signal.

11 . The gate driving circuit of claim 10 , wherein the auxiliary power line and the first power line are a same line.

12 . The gate driving circuit of claim 10 , wherein the auxiliary power line and the first power line are different lines such that the auxiliary signal is different from the first power signal.

13 . The gate driving circuit of claim 10 , wherein the second auxiliary module further comprises:

a second auxiliary transistor, having a drain electrically connected to the gate of the second pull-down maintaining transistor, a source electrically connected to the auxiliary power line to receive the auxiliary signal, and a gate connected to a second control signal line to receive a second control signal;

wherein a gate of the first pull-down maintaining transistor is electrically connected to a first pull-down maintaining line to receive a first pull-down maintaining signal;

wherein the first pull-down maintaining signal is configured to turn on the first pull-down maintaining transistor to allow the first power signal to control the voltage level of the first node, the first pull-down maintaining signal comprises alternatively-arranged high voltage levels and low voltage levels, and the high voltage levels of the first pull-down maintaining signal are corresponding to the low voltage levels of the second pull-down maintaining signal; and

wherein the second control signal is identical to the first pull-down maintaining signal.

14 . The gate driving circuit of claim 10 , wherein the first auxiliary module comprises:

a control signal line, electrically connected to the gate of the first pull-down maintaining transistor and carrying a control signal;

wherein the control signal comprises a plurality of effective voltage levels arranged at intervals, and each of the effective voltage levels is configured to control the on/off state of the first pull-down maintaining transistor.

15 . A display panel, comprising a gate driving circuit comprising a plurality of cascaded gate driving units, each of the gate driving unit comprising:

a pull-up control module;

a pull-up module, electrically connected to the pull-up control module through a first node and electrically connected to a scan line;

a pull-down module, electrically connected to the scan line;

a first pull-down maintaining module, comprising:

a first pull-down maintaining transistor, having a drain connected to the first node; and

a first auxiliary module, electrically connected to a gate of the first pull-down maintaining transistor, configured to turn off the first pull-down maintaining transistor in on-state; and

a second pull-down maintaining module, comprising:

a second pull-down maintaining transistor, having a gate electrically connected to a second pull-down maintaining line to receive a second pull-down maintaining signal, a source electrically connected to the first pull-down maintaining transistor and a first power line to receive a first power signal, and a drain electrically connected to the first node;

wherein the first pull-down maintaining transistor and the second pull-down maintaining transistor are alternatively turned on, and the first pull-down maintaining transistor and the second pull-down maintaining transistor are alternatively turned off;

wherein the first pull-down maintaining module further comprises:

a first converting module, electrically connected to the first node and the gate of the first pull-down maintaining transistor, configured to turn on the first pull-down maintaining transistor;

wherein the first auxiliary module comprises:

a first auxiliary transistor, having a drain electrically connected to the gate of the first pull-down maintaining transistor, a source electrically connected to an auxiliary power line to receive an auxiliary signal, and a gate connected to a first control signal line to receive a first control signal;

wherein the first control signal is configured to turn on the first auxiliary transistor to allow the auxiliary signal to control the on/off state of the first pull-down maintaining transistor; and

wherein the second pull-down maintaining signal comprises alternatively-arranged high voltage levels and low voltage levels, the second pull-down maintaining signal is configured to turn on the second pull-down maintaining transistor to allow the first power signal to control a voltage level of the first node, and the first control signal is identical to the second pull-down maintaining signal.

16 . The display panel of claim 15 , wherein the auxiliary power line and the first power line are a same line.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (18)