Display panel includes a plurality of high-potential voltage lines and low-potential voltage lines on different sides of a gate driving circuit and display device
A display panel having a display area where a plurality of subpixels are disposed, a gate driving circuit disposed in a non-display area outside the display area to supply a plurality of scan signals to the plurality of subpixels, a plurality of gate high-potential voltage lines which are disposed in a side of the gate driving circuit for transferring a plurality of gate high-potential voltages, a plurality of gate low-potential voltage lines which are disposed in other side of the gate driving circuit for transferring a plurality of gate low-potential voltages, and a plurality of gate low-potential voltage connection lines which are extended through a central area of the gate driving circuit for transferring the plurality of gate low-potential voltages to the gate driving circuit.
1 . A display panel, comprising:
a display area where a plurality of subpixels are disposed;
a gate driving circuit disposed in a non-display area outside the display area to supply a plurality of scan signals to the plurality of subpixels, and including a plurality of gate driving panel circuits configured to generate at least one scan signal;
a plurality of gate high-potential voltage lines which are disposed in a first side of the gate driving circuit for transferring a plurality of gate high-potential voltages;
a plurality of gate low-potential voltage lines which are disposed in a second side of the gate driving circuit for transferring a plurality of gate low-potential voltages; and
a plurality of gate low-potential voltage connection lines which extend through a central area of the gate driving circuit for transferring the plurality of gate low-potential voltages to the gate driving circuit,
wherein the plurality of gate driving panel circuits include:
an output buffer block configured to output the at least one scan signal based on voltage states of a first node and a second node;
a logic block configured to control voltages of the first node and the second node; and
a real-time sensing control block configured to control the logic block to perform a real-time sensing driving operation.
2 . The display panel of claim 1 , wherein the first node is a Q node for controlling a pull-up transistor of the output buffer block.
3 . The display panel of claim 1 , wherein the second node is a QB node for controlling a pull-down transistor of the output buffer block.
4 . The display panel of claim 1 , wherein the output buffer block includes:
a carry output buffer configured to output a carry signal; and
a scan output buffer configured to output the at least one scan signal.
5 . The display panel of claim 4 , wherein the scan output buffer is arranged in a symmetrical structure with respect to the central area.
6 . The display panel of claim 4 , wherein the scan output buffer is arranged in a symmetrical structure including a left side and a right side.
7 . The display panel of claim 5 , wherein the plurality of gate low-potential voltage lines include
a first gate low-potential voltage line for transferring a first gate low-potential voltage to the scan output buffer;
a second gate low-potential voltage line for transferring a second gate low-potential voltage to the logic block; and
a third gate low-potential voltage line for transferring a third gate low-potential voltage to the logic block and the carry output buffer.
8 . The display panel of claim 7 , wherein the first gate low-potential voltage line is disposed closest to the gate driving panel circuit among the plurality of gate low-potential voltage lines.
9 . The display panel of claim 7 , wherein the second gate low-potential voltage has a level higher than the third gate low-potential voltage.
10 . The display panel of claim 7 , wherein the plurality of gate low-potential voltage connection lines include:
a plurality of first gate low-potential voltage connection lines which are disposed in the central area for transferring the first gate low-potential voltage to the scan output buffer;
a second gate low-potential voltage connection line which is disposed in the central area for transferring the second gate low-potential voltage to the logic block; and
a third gate low-potential voltage connection line which is disposed in the central area for transferring the third gate low-potential voltage to the logic block and the carry output buffer.
11 . The display panel of claim 10 , wherein the plurality of first gate low-potential voltage connection lines are disposed close to the scan output buffer.
12 . The display panel of claim 10 , wherein the second gate low-potential voltage connection line and the third gate low-potential voltage connection line are disposed between the plurality of first gate low-potential voltage connection lines.
13 . A display device, comprising:
a display panel including a plurality of subpixels;
a gate driving circuit configured to supply a plurality of scan signals to the display panel through a plurality of gate lines, and including a plurality of gate driving panel circuits configured to generate at least one scan signal;
a data driving circuit configured to supply a plurality of data voltages to the display panel through a plurality of data lines; and
a timing controller configured to control the gate driving circuit and the data driving circuit,
wherein the display panel further includes:
a plurality of gate high-potential voltage lines which are disposed in a first side of the gate driving circuit for transferring a plurality of gate high-potential voltages;
a plurality of gate low-potential voltage lines which are disposed in a second side of the gate driving circuit for transferring a plurality of gate low-potential voltages; and
a plurality of gate low-potential voltage connection lines which extend through a central area of the gate driving circuit for transferring the plurality of gate low-potential voltages to the gate driving circuit,
wherein the plurality of gate driving panel circuits include:
an output buffer block configured to output the at least one scan signal based on voltage states of a first node and a second node;
a logic block configured to control voltages of the first node and the second node; and
a real-time sensing control block configured to control the logic block to perform a real-time sensing driving operation.
14 . A display device, comprising:
a display panel which includes a display area where a plurality of subpixels are disposed and a gate driving circuit disposed in a non-display area outside the display area to supply a plurality of scan signals to the plurality of subpixels;
a data driving circuit configured to supply a plurality of data voltages to the display panel through a plurality of data lines; and
a timing controller configured to control the gate driving circuit and the data driving circuit,
wherein the display panel further includes:
a plurality of gate high-potential voltage lines which are disposed in a first side of the gate driving circuit for transferring a plurality of gate high-potential voltages;
a plurality of gate low-potential voltage lines which are disposed in a second side of the gate driving circuit for transferring a plurality of gate low-potential voltages; and
a plurality of gate low-potential voltage connection lines which extend through a central area of the gate driving circuit for transferring the plurality of gate low-potential voltages to the gate driving circuit,
wherein the gate driving circuit includes a plurality of gate driving panel circuits configured to generate at least one scan signal,
wherein the plurality of gate driving panel circuits include:
an output buffer block configured to output the at least one scan signal based on voltage states of a first node and a second node;
a logic block configured to control voltages of the first node and the second node; and
a real-time sensing control block configured to control the logic block to perform a real-time sensing driving operation.